| Message ID | 20220806141059.2498226-3-vladimir.oltean@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Validate OF nodes for DSA shared ports | expand |
On Sat Aug 06 2022, Vladimir Oltean wrote: > Looking at hellcreek_phylink_get_caps(), I see that depending on whether > is_100_mbits is set, speeds of 1G or of 100M will be advertised. The > de1soc_r1_pdata sets is_100_mbits to true. > > The PHY modes declared in the capabilities are MII, RGMII and GMII. GMII > doesn't support 100Mbps, and as for RGMII, it would be a bit implausible > to me to support this PHY mode but limit it to only 25 MHz. So I've > settled on MII as a phy-mode in the example, and a fixed-link of > 100Mbps. > > As a side note, there exists such a thing as "rev-mii", because the MII > protocol is asymmetric, and "mii" is the designation for the MAC side > (expected to be connected to a PHY), and "rev-mii" is the designation > for the PHY side (expected to be connected to a MAC). I wonder whether > "mii" or "rev-mii" should actually be used here, since this is a CPU > port and presumably connected to another MAC. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de>
On Sat, 06 Aug 2022 17:10:51 +0300, Vladimir Oltean wrote: > Looking at hellcreek_phylink_get_caps(), I see that depending on whether > is_100_mbits is set, speeds of 1G or of 100M will be advertised. The > de1soc_r1_pdata sets is_100_mbits to true. > > The PHY modes declared in the capabilities are MII, RGMII and GMII. GMII > doesn't support 100Mbps, and as for RGMII, it would be a bit implausible > to me to support this PHY mode but limit it to only 25 MHz. So I've > settled on MII as a phy-mode in the example, and a fixed-link of > 100Mbps. > > As a side note, there exists such a thing as "rev-mii", because the MII > protocol is asymmetric, and "mii" is the designation for the MAC side > (expected to be connected to a PHY), and "rev-mii" is the designation > for the PHY side (expected to be connected to a MAC). I wonder whether > "mii" or "rev-mii" should actually be used here, since this is a CPU > port and presumably connected to another MAC. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > v2->v3: patch is new > > .../devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml b/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml index 228683773151..1ff44dd68a61 100644 --- a/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml +++ b/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml @@ -93,6 +93,12 @@ examples: reg = <0>; label = "cpu"; ethernet = <&gmac0>; + phy-mode = "mii"; + + fixed-link { + speed = <100>; + full-duplex; + }; }; port@2 {
Looking at hellcreek_phylink_get_caps(), I see that depending on whether is_100_mbits is set, speeds of 1G or of 100M will be advertised. The de1soc_r1_pdata sets is_100_mbits to true. The PHY modes declared in the capabilities are MII, RGMII and GMII. GMII doesn't support 100Mbps, and as for RGMII, it would be a bit implausible to me to support this PHY mode but limit it to only 25 MHz. So I've settled on MII as a phy-mode in the example, and a fixed-link of 100Mbps. As a side note, there exists such a thing as "rev-mii", because the MII protocol is asymmetric, and "mii" is the designation for the MAC side (expected to be connected to a PHY), and "rev-mii" is the designation for the PHY side (expected to be connected to a MAC). I wonder whether "mii" or "rev-mii" should actually be used here, since this is a CPU port and presumably connected to another MAC. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> --- v2->v3: patch is new .../devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml | 6 ++++++ 1 file changed, 6 insertions(+)