diff mbox series

[v4,07/10] riscv: dts: r9a07g043: Add placeholder nodes

Message ID 20220920184904.90495-8-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Add support for Renesas RZ/Five SoC | expand

Commit Message

Lad, Prabhakar Sept. 20, 2022, 6:49 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.

This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier board
DTSIs([0] and [1]).

As the RZ/G2UL SMARC EVK enables almost all the blocks supported by the
SoC and whereas for the RZ/Five SMARC EVK we will gradually be enabling
the blocks as a result we are adding the placeholder nodes to avoid DTB
compilation errors (currently we dont have support in DTC to delete the
reference nodes without actual nodes).

[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3 -> v4
* Dropped status and reg-names properties
* Updated the commit message
* Note sbc node is not enabled in RZ/G2UL SMARC EVK but will be soon
  enabled so added a placeholder for this too.

v2 -> v3
* New patch
---
 arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 150 +++++++++++++++++++++
 1 file changed, 150 insertions(+)

Comments

Biju Das Sept. 20, 2022, 7:21 p.m. UTC | #1 
Hi Prabhakar,

Thanks for the patch.

> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
> 
> This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> board DTSIs([0] and [1]).

Just a question, 

Why can't we reuse SoC dtsi as well, as 90% of the SoC nodes are same?

Split common stuff from arch/arm/boot/dts/renesas/r9a07g043.dtsi 

and add ARM specific CPU, IRQ to arch/arm/boot/dts/renesas/r9a07g043u.dtsi

RISC-V specific CPU, IRQ to arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

Both r9a07g043{u,f} dtsi will add common dtsi.


Cheers,
Biju


> 
> As the RZ/G2UL SMARC EVK enables almost all the blocks supported by
> the SoC and whereas for the RZ/Five SMARC EVK we will gradually be
> enabling the blocks as a result we are adding the placeholder nodes to
> avoid DTB compilation errors (currently we dont have support in DTC to
> delete the reference nodes without actual nodes).
> 
> [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3 -> v4
> * Dropped status and reg-names properties
> * Updated the commit message
> * Note sbc node is not enabled in RZ/G2UL SMARC EVK but will be soon
>   enabled so added a placeholder for this too.
> 
> v2 -> v3
> * New patch
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 150
> +++++++++++++++++++++
>  1 file changed, 150 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> index fb6733f3cc2b..d90d263b1b13 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -13,6 +13,14 @@ / {
>  	#address-cells = <2>;
>  	#size-cells = <2>;
> 
> +	audio_clk1: audio1-clk {
> +		/* placeholder */
> +	};
> +
> +	audio_clk2: audio2-clk {
> +		/* placeholder */
> +	};
> +
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -54,6 +62,19 @@ soc: soc {
>  		#size-cells = <2>;
>  		ranges;
> 
> +		ssi1: ssi@1004a000 {
> +			reg = <0 0x1004a000 0 0x400>;
> +			#sound-dai-cells = <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		spi1: spi@1004b000 {
> +			reg = <0 0x1004b000 0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
>  		scif0: serial@1004b800 {
>  			compatible = "renesas,scif-r9a07g043",
>  				     "renesas,scif-r9a07g044";
> @@ -73,6 +94,41 @@ scif0: serial@1004b800 {
>  			status = "disabled";
>  		};
> 
> +		canfd: can@10050000 {
> +			reg = <0 0x10050000 0 0x8000>;
> +
> +			/* placeholder */
> +		};
> +
> +		i2c0: i2c@10058000 {
> +			reg = <0 0x10058000 0 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			/* placeholder */
> +		};
> +
> +		i2c1: i2c@10058400 {
> +			reg = <0 0x10058400 0 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		adc: adc@10059000 {
> +			reg = <0 0x10059000 0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
> +		sbc: spi@10060000 {
> +			reg = <0 0x10060000 0 0x10000>,
> +			      <0 0x20000000 0 0x10000000>,
> +			      <0 0x10070000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
>  		cpg: clock-controller@11010000 {
>  			compatible = "renesas,r9a07g043-cpg";
>  			reg = <0 0x11010000 0 0x10000>;
> @@ -104,6 +160,82 @@ pinctrl: pinctrl@11030000 {
>  				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
>  		};
> 
> +		sdhi0: mmc@11c00000 {
> +			reg = <0x0 0x11c00000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
> +		sdhi1: mmc@11c10000 {
> +			reg = <0x0 0x11c10000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
> +		eth0: ethernet@11c20000 {
> +			reg = <0 0x11c20000 0 0x10000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		eth1: ethernet@11c30000 {
> +			reg = <0 0x11c30000 0 0x10000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* placeholder */
> +		};
> +
> +		phyrst: usbphy-ctrl@11c40000 {
> +			reg = <0 0x11c40000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
> +		ohci0: usb@11c50000 {
> +			reg = <0 0x11c50000 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		ohci1: usb@11c70000 {
> +			reg = <0 0x11c70000 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		ehci0: usb@11c50100 {
> +			reg = <0 0x11c50100 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		ehci1: usb@11c70100 {
> +			reg = <0 0x11c70100 0 0x100>;
> +
> +			/* placeholder */
> +		};
> +
> +		usb2_phy0: usb-phy@11c50200 {
> +			reg = <0 0x11c50200 0 0x700>;
> +
> +			/* placeholder */
> +		};
> +
> +		usb2_phy1: usb-phy@11c70200 {
> +			reg = <0 0x11c70200 0 0x700>;
> +
> +			/* placeholder */
> +		};
> +
> +		hsusb: usb@11c60000 {
> +			reg = <0 0x11c60000 0 0x10000>;
> +
> +			/* placeholder */
> +		};
> +
>  		plic: interrupt-controller@12c00000 {
>  			compatible = "renesas,r9a07g043-plic",
> "andestech,nceplic100";
>  			#interrupt-cells = <2>;
> @@ -116,5 +248,23 @@ plic: interrupt-controller@12c00000 {
>  			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>  			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
>  		};
> +
> +		wdt0: watchdog@12800800 {
> +			reg = <0 0x12800800 0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
> +		ostm1: timer@12801400 {
> +			reg = <0x0 0x12801400 0x0 0x400>;
> +
> +			/* placeholder */
> +		};
> +
> +		ostm2: timer@12801800 {
> +			reg = <0x0 0x12801800 0x0 0x400>;
> +
> +			/* placeholder */
> +		};
>  	};
>  };
> --
> 2.25.1
Biju Das Sept. 20, 2022, 7:26 p.m. UTC | #2 
Just ignore my mail, As I realised IRQ property in each node will be a problem.

Cheers,
Biju

> -----Original Message-----
> From: Biju Das
> Sent: 20 September 2022 20:22
> To: Prabhakar <prabhakar.csengg@gmail.com>; Rob Herring
> <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Paul Walmsley
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> Albert Ou <aou@eecs.berkeley.edu>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Magnus Damm <magnus.damm@gmail.com>; Conor
> Dooley <conor.dooley@microchip.com>
> Cc: Heiko Stuebner <heiko@sntech.de>; Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com>; Atish Patra
> <atishp@rivosinc.com>; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> renesas-soc@vger.kernel.org; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> Subject: RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> nodes
> 
> Hi Prabhakar,
> 
> Thanks for the patch.
> 
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
> >
> > This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> > board DTSIs([0] and [1]).
> 
> Just a question,
> 
> Why can't we reuse SoC dtsi as well, as 90% of the SoC nodes are same?
> 
> Split common stuff from arch/arm/boot/dts/renesas/r9a07g043.dtsi
> 
> and add ARM specific CPU, IRQ to
> arch/arm/boot/dts/renesas/r9a07g043u.dtsi
> 
> RISC-V specific CPU, IRQ to
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> 
> Both r9a07g043{u,f} dtsi will add common dtsi.
> 
> 
> Cheers,
> Biju
> 
> 
> >
> > As the RZ/G2UL SMARC EVK enables almost all the blocks supported by
> > the SoC and whereas for the RZ/Five SMARC EVK we will gradually be
> > enabling the blocks as a result we are adding the placeholder nodes
> to
> > avoid DTB compilation errors (currently we dont have support in DTC
> to
> > delete the reference nodes without actual nodes).
> >
> > [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> > ---
> > v3 -> v4
> > * Dropped status and reg-names properties
> > * Updated the commit message
> > * Note sbc node is not enabled in RZ/G2UL SMARC EVK but will be soon
> >   enabled so added a placeholder for this too.
> >
> > v2 -> v3
> > * New patch
> > ---
> >  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 150
> > +++++++++++++++++++++
> >  1 file changed, 150 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > index fb6733f3cc2b..d90d263b1b13 100644
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -13,6 +13,14 @@ / {
> >  	#address-cells = <2>;
> >  	#size-cells = <2>;
> >
> > +	audio_clk1: audio1-clk {
> > +		/* placeholder */
> > +	};
> > +
> > +	audio_clk2: audio2-clk {
> > +		/* placeholder */
> > +	};
> > +
> >  	cpus {
> >  		#address-cells = <1>;
> >  		#size-cells = <0>;
> > @@ -54,6 +62,19 @@ soc: soc {
> >  		#size-cells = <2>;
> >  		ranges;
> >
> > +		ssi1: ssi@1004a000 {
> > +			reg = <0 0x1004a000 0 0x400>;
> > +			#sound-dai-cells = <0>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		spi1: spi@1004b000 {
> > +			reg = <0 0x1004b000 0 0x400>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> >  		scif0: serial@1004b800 {
> >  			compatible = "renesas,scif-r9a07g043",
> >  				     "renesas,scif-r9a07g044";
> > @@ -73,6 +94,41 @@ scif0: serial@1004b800 {
> >  			status = "disabled";
> >  		};
> >
> > +		canfd: can@10050000 {
> > +			reg = <0 0x10050000 0 0x8000>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		i2c0: i2c@10058000 {
> > +			reg = <0 0x10058000 0 0x400>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			/* placeholder */
> > +		};
> > +
> > +		i2c1: i2c@10058400 {
> > +			reg = <0 0x10058400 0 0x400>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		adc: adc@10059000 {
> > +			reg = <0 0x10059000 0 0x400>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		sbc: spi@10060000 {
> > +			reg = <0 0x10060000 0 0x10000>,
> > +			      <0 0x20000000 0 0x10000000>,
> > +			      <0 0x10070000 0 0x10000>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> >  		cpg: clock-controller@11010000 {
> >  			compatible = "renesas,r9a07g043-cpg";
> >  			reg = <0 0x11010000 0 0x10000>;
> > @@ -104,6 +160,82 @@ pinctrl: pinctrl@11030000 {
> >  				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> >  		};
> >
> > +		sdhi0: mmc@11c00000 {
> > +			reg = <0x0 0x11c00000 0 0x10000>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		sdhi1: mmc@11c10000 {
> > +			reg = <0x0 0x11c10000 0 0x10000>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		eth0: ethernet@11c20000 {
> > +			reg = <0 0x11c20000 0 0x10000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		eth1: ethernet@11c30000 {
> > +			reg = <0 0x11c30000 0 0x10000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		phyrst: usbphy-ctrl@11c40000 {
> > +			reg = <0 0x11c40000 0 0x10000>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		ohci0: usb@11c50000 {
> > +			reg = <0 0x11c50000 0 0x100>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		ohci1: usb@11c70000 {
> > +			reg = <0 0x11c70000 0 0x100>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		ehci0: usb@11c50100 {
> > +			reg = <0 0x11c50100 0 0x100>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		ehci1: usb@11c70100 {
> > +			reg = <0 0x11c70100 0 0x100>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		usb2_phy0: usb-phy@11c50200 {
> > +			reg = <0 0x11c50200 0 0x700>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		usb2_phy1: usb-phy@11c70200 {
> > +			reg = <0 0x11c70200 0 0x700>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		hsusb: usb@11c60000 {
> > +			reg = <0 0x11c60000 0 0x10000>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> >  		plic: interrupt-controller@12c00000 {
> >  			compatible = "renesas,r9a07g043-plic",
> "andestech,nceplic100";
> >  			#interrupt-cells = <2>;
> > @@ -116,5 +248,23 @@ plic: interrupt-controller@12c00000 {
> >  			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> >  			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> >  		};
> > +
> > +		wdt0: watchdog@12800800 {
> > +			reg = <0 0x12800800 0 0x400>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		ostm1: timer@12801400 {
> > +			reg = <0x0 0x12801400 0x0 0x400>;
> > +
> > +			/* placeholder */
> > +		};
> > +
> > +		ostm2: timer@12801800 {
> > +			reg = <0x0 0x12801800 0x0 0x400>;
> > +
> > +			/* placeholder */
> > +		};
> >  	};
> >  };
> > --
> > 2.25.1
Lad, Prabhakar Sept. 20, 2022, 8:51 p.m. UTC | #3 
Hi Biju,

On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
>
> Just ignore my mail, As I realised IRQ property in each node will be a problem.
>
Yes the IRQ numbers are different (offset of 32) along with the IRQ parent.

Refer this thread [0] where other SoC vendors have similar issues,
maybe in future when DTC becomes more clever we can use single SoC
DTSI for both.

[0] https://lore.kernel.org/lkml/CAMuHMdUMM9H4jLJ8-zOz9SXoqmK-s4zRWzGCsU8jt_sDgY1h+Q@mail.gmail.com/

Cheers,
Prabhakar
Biju Das Sept. 21, 2022, 5:22 a.m. UTC | #4 
Hi Prabhakar,

> Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> nodes
> 
> Hi Biju,
> 
> On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> >
> > Just ignore my mail, As I realised IRQ property in each node will be
> a problem.
> >
> Yes the IRQ numbers are different (offset of 32) along with the IRQ
> parent.
> 
> Refer this thread [0] where other SoC vendors have similar issues,
> maybe in future when DTC becomes more clever we can use single SoC
> DTSI for both.

Not sure, May be the macro suggestion mentioned in that thread will work for us??
As it is just only the interrupt properties that differ which is
handled in macro. A Generic macro in common dtsi which is
expanded in RISCV or arm64 specific dtsi to get proper one??

Cheers,
Biju
Geert Uytterhoeven Sept. 21, 2022, 7:49 a.m. UTC | #5 
Hi Biju,

On Wed, Sep 21, 2022 at 7:22 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> > nodes
> > On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Just ignore my mail, As I realised IRQ property in each node will be
> > a problem.
> > >
> > Yes the IRQ numbers are different (offset of 32) along with the IRQ
> > parent.
> >
> > Refer this thread [0] where other SoC vendors have similar issues,
> > maybe in future when DTC becomes more clever we can use single SoC
> > DTSI for both.
>
> Not sure, May be the macro suggestion mentioned in that thread will work for us??
> As it is just only the interrupt properties that differ which is
> handled in macro. A Generic macro in common dtsi which is
> expanded in RISCV or arm64 specific dtsi to get proper one??

I brought it up with the DT people in a separate thread[1].
Please continue the discussion there.
Thanks!

[1] https://lore.kernel.org/r/CAMuHMdUPm36RsxHdVwspR3NCAR3C507AyB6R65W42N2gXWq0ag@mail.gmail.com

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
index fb6733f3cc2b..d90d263b1b13 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -13,6 +13,14 @@  / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	audio_clk1: audio1-clk {
+		/* placeholder */
+	};
+
+	audio_clk2: audio2-clk {
+		/* placeholder */
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -54,6 +62,19 @@  soc: soc {
 		#size-cells = <2>;
 		ranges;
 
+		ssi1: ssi@1004a000 {
+			reg = <0 0x1004a000 0 0x400>;
+			#sound-dai-cells = <0>;
+
+			/* placeholder */
+		};
+
+		spi1: spi@1004b000 {
+			reg = <0 0x1004b000 0 0x400>;
+
+			/* placeholder */
+		};
+
 		scif0: serial@1004b800 {
 			compatible = "renesas,scif-r9a07g043",
 				     "renesas,scif-r9a07g044";
@@ -73,6 +94,41 @@  scif0: serial@1004b800 {
 			status = "disabled";
 		};
 
+		canfd: can@10050000 {
+			reg = <0 0x10050000 0 0x8000>;
+
+			/* placeholder */
+		};
+
+		i2c0: i2c@10058000 {
+			reg = <0 0x10058000 0 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			/* placeholder */
+		};
+
+		i2c1: i2c@10058400 {
+			reg = <0 0x10058400 0 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* placeholder */
+		};
+
+		adc: adc@10059000 {
+			reg = <0 0x10059000 0 0x400>;
+
+			/* placeholder */
+		};
+
+		sbc: spi@10060000 {
+			reg = <0 0x10060000 0 0x10000>,
+			      <0 0x20000000 0 0x10000000>,
+			      <0 0x10070000 0 0x10000>;
+
+			/* placeholder */
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a07g043-cpg";
 			reg = <0 0x11010000 0 0x10000>;
@@ -104,6 +160,82 @@  pinctrl: pinctrl@11030000 {
 				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
 		};
 
+		sdhi0: mmc@11c00000 {
+			reg = <0x0 0x11c00000 0 0x10000>;
+
+			/* placeholder */
+		};
+
+		sdhi1: mmc@11c10000 {
+			reg = <0x0 0x11c10000 0 0x10000>;
+
+			/* placeholder */
+		};
+
+		eth0: ethernet@11c20000 {
+			reg = <0 0x11c20000 0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* placeholder */
+		};
+
+		eth1: ethernet@11c30000 {
+			reg = <0 0x11c30000 0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* placeholder */
+		};
+
+		phyrst: usbphy-ctrl@11c40000 {
+			reg = <0 0x11c40000 0 0x10000>;
+
+			/* placeholder */
+		};
+
+		ohci0: usb@11c50000 {
+			reg = <0 0x11c50000 0 0x100>;
+
+			/* placeholder */
+		};
+
+		ohci1: usb@11c70000 {
+			reg = <0 0x11c70000 0 0x100>;
+
+			/* placeholder */
+		};
+
+		ehci0: usb@11c50100 {
+			reg = <0 0x11c50100 0 0x100>;
+
+			/* placeholder */
+		};
+
+		ehci1: usb@11c70100 {
+			reg = <0 0x11c70100 0 0x100>;
+
+			/* placeholder */
+		};
+
+		usb2_phy0: usb-phy@11c50200 {
+			reg = <0 0x11c50200 0 0x700>;
+
+			/* placeholder */
+		};
+
+		usb2_phy1: usb-phy@11c70200 {
+			reg = <0 0x11c70200 0 0x700>;
+
+			/* placeholder */
+		};
+
+		hsusb: usb@11c60000 {
+			reg = <0 0x11c60000 0 0x10000>;
+
+			/* placeholder */
+		};
+
 		plic: interrupt-controller@12c00000 {
 			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
 			#interrupt-cells = <2>;
@@ -116,5 +248,23 @@  plic: interrupt-controller@12c00000 {
 			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
 			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
 		};
+
+		wdt0: watchdog@12800800 {
+			reg = <0 0x12800800 0 0x400>;
+
+			/* placeholder */
+		};
+
+		ostm1: timer@12801400 {
+			reg = <0x0 0x12801400 0x0 0x400>;
+
+			/* placeholder */
+		};
+
+		ostm2: timer@12801800 {
+			reg = <0x0 0x12801800 0x0 0x400>;
+
+			/* placeholder */
+		};
 	};
 };