From patchwork Mon Jan 16 10:39:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13102883 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35769C54EBE for ; Mon, 16 Jan 2023 10:38:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230386AbjAPKiH (ORCPT ); Mon, 16 Jan 2023 05:38:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230387AbjAPKhz (ORCPT ); Mon, 16 Jan 2023 05:37:55 -0500 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B3031BAFD; Mon, 16 Jan 2023 02:37:35 -0800 (PST) Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 2BAD51BF20D; Mon, 16 Jan 2023 10:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1673865454; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=otK04t6Fq+0COownezUclLPHt9Yq8LgEt2fdJEWCBeY=; b=SgVpIa9+7N5kErKew4ZANdCP3OgDdChVG7HEXYslpXSzH7kvthC+fDHeFxhnov9U3/LWVX VjRKdfUkztdgeLWQV1qbhW2EjzVSlFpO8oSVajOsieEF5LJzu54hu5F81H9DiiyJF7NXv0 wusfQa+cj2Gy/i3aL23RJ+Zv0wh4sjwGsaBGQec3wlbJNGwMlq8kPckzFNJi2DRSbVixKU LzcPKzCgm5A74SLyL/SVLgE5+cDHuffnhAYISWss/MI41KnD23sfO3JYTXtgxzKCk+YoIG Z1EEoADo6NCN6Ok1TK6/zLEBuVeLaGIXzAJkzXKCE6IYT0o35UVIu/nQVDb6UQ== From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Sergey Shtylyov , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Russell King , Wong Vee Khee , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Kurt Kanzenbach , Revanth Kumar Uppala , Tan Tee Min Cc: Thomas Petazzoni , Herve Codina , =?utf-8?q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Mohammad Athari Bin Ismail , Jon Hunter , netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next 3/6] net: stmmac: start phylink before setting up hardware Date: Mon, 16 Jan 2023 11:39:23 +0100 Message-Id: <20230116103926.276869-4-clement.leger@bootlin.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116103926.276869-1-clement.leger@bootlin.com> References: <20230116103926.276869-1-clement.leger@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The stmmac on the Renesas RZ/N1 platform is connected to the PCS which must be configured to provide a correct RGMII RX clock to the stmmac IP. Without the RX clock, the driver will fail to initialize the hardware (more specifically, the driver will report it fails to reset DMA). In order to fix that, start phylink mecanism before setting up hardware. Signed-off-by: Clément Léger --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index f2247b8cf0a3..88c941003855 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3818,6 +3818,12 @@ static int __stmmac_open(struct net_device *dev, } } + /* We need to setup the phy & PCS before accessing the stmmac registers + * because in some cases (RZ/N1), if the stmmac IP is not clocked by the + * PCS, hardware init will fail because it lacks a RGMII RX clock. + */ + phylink_start(priv->phylink); + ret = stmmac_hw_setup(dev, true); if (ret < 0) { netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); @@ -3826,7 +3832,6 @@ static int __stmmac_open(struct net_device *dev, stmmac_init_coalesce(priv); - phylink_start(priv->phylink); /* We may have called phylink_speed_down before */ phylink_speed_up(priv->phylink);