| Message ID | 20230222234212.5461-3-laurent.pinchart+renesas@ideasonboard.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 944eb068879f297af5470b7d9ffc58d7be3c6df3 |
| Delegated to: | Kieran Bingham |
| Headers | show |
| Series | drm: rcar-du: Fix more invalid register writes | expand |
On 23/02/2023 01:42, Laurent Pinchart wrote: > The DORCR register controls the routing of clocks and data between DU > channels within a group. For groups that contain a single channel, > there's no routing option to control, and some fields of the register > are then reserved. On Gen2 those reserved fields are documented as > required to be set to 0, while on Gen3 and newer the PG1T, DK1S and PG1D > reserved fields must be set to 1. > > The DU driver initializes the DORCR register in rcar_du_group_setup(), > where it ignores the PG1T, DK1S and PG1D, and then configures those > fields to the correct value in rcar_du_group_set_routing(). This hasn't > been shown to cause any issue, but prevents certifying that the driver > complies with the documentation in safety-critical use cases. > > As there is no reasonable change that the documentation will be updated > to clarify that those reserved fields can be written to 0 temporarily > before starting the hardware, make sure that the registers are always > set to valid values. > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > --- > drivers/gpu/drm/rcar-du/rcar_du_group.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Tomi
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index b5950749d68a..2ccd2581f544 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -138,6 +138,7 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) { struct rcar_du_device *rcdu = rgrp->dev; u32 defr7 = DEFR7_CODE; + u32 dorcr; /* Enable extended features */ rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE); @@ -174,8 +175,15 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) /* * Use DS1PR and DS2PR to configure planes priorities and connects the * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. + * + * Groups that have a single channel have a hardcoded configuration. On + * Gen3 and newer, the documentation requires PG1T, DK1S and PG1D_DS1 to + * always be set in this case. */ - rcar_du_group_write(rgrp, DORCR, DORCR_PG0D_DS0 | DORCR_DPRS); + dorcr = DORCR_PG0D_DS0 | DORCR_DPRS; + if (rcdu->info->gen >= 3 && rgrp->num_crtcs == 1) + dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1; + rcar_du_group_write(rgrp, DORCR, dorcr); /* Apply planes to CRTCs association. */ mutex_lock(&rgrp->lock);
The DORCR register controls the routing of clocks and data between DU channels within a group. For groups that contain a single channel, there's no routing option to control, and some fields of the register are then reserved. On Gen2 those reserved fields are documented as required to be set to 0, while on Gen3 and newer the PG1T, DK1S and PG1D reserved fields must be set to 1. The DU driver initializes the DORCR register in rcar_du_group_setup(), where it ignores the PG1T, DK1S and PG1D, and then configures those fields to the correct value in rcar_du_group_set_routing(). This hasn't been shown to cause any issue, but prevents certifying that the driver complies with the documentation in safety-critical use cases. As there is no reasonable change that the documentation will be updated to clarify that those reserved fields can be written to 0 temporarily before starting the hardware, make sure that the registers are always set to valid values. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> --- drivers/gpu/drm/rcar-du/rcar_du_group.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)