diff mbox series

[DO,NOT,APPLY,v7,09/10] pinctrl: renesas: rzg2l-poeg: output-disable request by external pin

Message ID 20230328101011.185594-10-biju.das.jz@bp.renesas.com (mailing list archive)
State RFC
Delegated to: Geert Uytterhoeven
Headers show
Series Add RZ/G2L POEG support | expand

Commit Message

Biju Das March 28, 2023, 10:10 a.m. UTC 
Add support for output-disable request by external pin.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 9 +++++++++
 include/linux/pinctrl/rzg2l-poeg.h        | 2 ++
 2 files changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
index 7576f756af3c..5d93a0be33f3 100644
--- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
+++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
@@ -15,13 +15,16 @@ 
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/pwm/rzg2l-gpt.h>
+#include <linux/pinctrl/rzg2l-poeg.h>
 #include <linux/poll.h>
 #include <linux/reset.h>
 #include <linux/wait.h>
 
 #define POEGG_IOCE	BIT(5)
+#define POEGG_PIDE	BIT(4)
 #define POEGG_SSF	BIT(3)
 #define POEGG_IOCF	BIT(1)
+#define POEGG_PIDF	BIT(0)
 
 #define RZG2L_POEG_MAX_INDEX		3
 
@@ -113,6 +116,9 @@  static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr)
 	if (val & POEGG_IOCF)
 		val &= ~POEGG_IOCF;
 
+	if (val & POEGG_PIDF)
+		val &= ~POEGG_PIDF;
+
 	rzg2l_poeg_write(chip, val);
 
 	return IRQ_HANDLED;
@@ -378,6 +384,9 @@  static int rzg2l_poeg_probe(struct platform_device *pdev)
 			assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true);
 			assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true);
 			break;
+		case POEG_EXT_PIN_CTRL:
+			rzg2l_poeg_write(chip, POEGG_PIDE);
+			break;
 		default:
 			ret = -EINVAL;
 			goto err_pm;
diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg2l-poeg.h
index 5441de7f3751..359849fea6a0 100644
--- a/include/linux/pinctrl/rzg2l-poeg.h
+++ b/include/linux/pinctrl/rzg2l-poeg.h
@@ -7,11 +7,13 @@ 
 #define RZG2L_GPT_DTEF	0
 #define RZG2L_GPT_OABHF	1
 #define RZG2L_GPT_OABLF	2
+#define RZG2L_POEG_EXT_PIN_CTRL	3
 
 #define RZG2L_POEG_USR_CTRL_ENABLE_CMD	0
 #define RZG2L_POEG_USR_CTRL_DISABLE_CMD	1
 #define RZG2L_POEG_GPT_CFG_IRQ_CMD		2
 #define RZG2L_POEG_GPT_FAULT_CLR_CMD		3
+#define RZG2L_POEG_EXT_PIN_CTRL_FAULT_CLR_CMD	4
 
 struct poeg_event {
 	__u32 gpt_disable_irq_status;