| Message ID | 20230726080832.120669-1-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: rz-smarc-common: Use versa3 clk for audio mclk | expand |
Hi Biji, On Wed, Jul 26, 2023 at 10:08 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz). > Replace this fixed clk with the programmable versa3 clk that can provide > the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and > 48kHz (with a clock of 12.2880MHz), based on audio sampling rate for > playback and record. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi > +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi > @@ -32,12 +32,6 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > - audio_mclock: audio_mclock { > - compatible = "fixed-clock"; > - #clock-cells = <0>; > - clock-frequency = <11289600>; > - }; > - > snd_rzg2l: sound { > compatible = "simple-audio-card"; > simple-audio-card,format = "i2s"; > @@ -55,7 +49,7 @@ cpu_dai: simple-audio-card,cpu { > }; > > codec_dai: simple-audio-card,codec { > - clocks = <&audio_mclock>; > + clocks = <&versa3 3>; The bindings do not mention the mapping from clock indices to actual outputs. According to Table 3. ("Output Source") in the 5P35023 datasheet, I would expect the mapping to be 0=REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2. But as AUDIO_MCK is sourced from SE2, that can't be correct? Oops, the mapping in the driver uses the order in the Block Diagram, which is the inverse... > sound-dai = <&wm8978>; > }; > }; > @@ -76,6 +70,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 { > gpios-states = <1>; > states = <3300000 1>, <1800000 0>; > }; > + > + x1_x2: xtal { X2 is a different 32768 kHz crystal. "xtal" is a too-generic node name, and may cause conflicts that are hard to debug . "x1: x1-clock {", cfr. "x2" in arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi? > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; > }; > > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi > @@ -20,6 +20,27 @@ &cpu_dai { > sound-dai = <&ssi1>; > }; > > +&i2c0 { Any specific reason you're not adding clock-frequency = <400000>; like is already present on the other SoMs? > + versa3: versa3@68 { > + compatible = "renesas,5p35023"; The rest LGTM, I didn't verify renesas,settings though. Note that to avoid introducing regressions, this patch has to be postponed until Versa3 clock support has reached upstream (v6.6-rc1?). Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index a7594ba3a998..bbad02bdd342 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -32,12 +32,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - audio_mclock: audio_mclock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - snd_rzg2l: sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -55,7 +49,7 @@ cpu_dai: simple-audio-card,cpu { }; codec_dai: simple-audio-card,codec { - clocks = <&audio_mclock>; + clocks = <&versa3 3>; sound-dai = <&wm8978>; }; }; @@ -76,6 +70,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 { gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; + + x1_x2: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &audio_clk1 { diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 68eab8e26bf2..b12fb20797c7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -105,6 +105,25 @@ &i2c3 { status = "okay"; + versa3: versa3@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1_x2>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <12288000>, <25000000>, + <12000000>, <11289600>, + <11289600>, <24000000>; + }; + wm8978: codec@1a { compatible = "wlf,wm8978"; #sound-dai-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 83fce96a2575..2608e471abed 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -121,6 +121,25 @@ &i2c2 { status = "okay"; + versa3: versa3@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1_x2>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <12288000>, <25000000>, + <12000000>, <11289600>, + <11289600>, <24000000>; + }; + wm8978: codec@1a { compatible = "wlf,wm8978"; #sound-dai-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 2a1331ed1a5c..f41dfdf61425 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -20,6 +20,27 @@ &cpu_dai { sound-dai = <&ssi1>; }; +&i2c0 { + versa3: versa3@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1_x2>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <12288000>, <25000000>, + <12000000>, <11289600>, + <11289600>, <24000000>; + }; +}; + &i2c1 { wm8978: codec@1a { compatible = "wlf,wm8978";
Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz). Replace this fixed clk with the programmable versa3 clk that can provide the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and 48kHz (with a clock of 12.2880MHz), based on audio sampling rate for playback and record. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/rz-smarc-common.dtsi | 14 ++++++------- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 19 +++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 19 +++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 21 +++++++++++++++++++ 4 files changed, 66 insertions(+), 7 deletions(-)