| Message ID | 20230824082501.87429-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Fix Versa3 clock mapping | expand |
Hi Biju, On Thu, Aug 24, 2023 at 10:25 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Fix the "assigned-clock-rates" for each clock output in the > example based on Table 3. ("Output Source") in the 5P35023 > datasheet(ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}). > > While at it, replace clocks phandle in the example from x1_x2->x1 as > X2 is a different 32768 kHz crystal. Thanks for your patch! > Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> This is not what I suggested. The bindings should document the meaning of the clock indices. > Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock generator bindings") This patch is not a critical fix. Gr{oetje,eeting}s, Geert
Hi Geert Uytterhoeven, Thanks for the feedback. > Subject: Re: [PATCH v4 1/4] dt-bindings: clock: versaclock3: Fix the > assigned-clock-rates > > Hi Biju, > > On Thu, Aug 24, 2023 at 10:25 AM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Fix the "assigned-clock-rates" for each clock output in the example > > based on Table 3. ("Output Source") in the 5P35023 > > datasheet(ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}). > > > > While at it, replace clocks phandle in the example from x1_x2->x1 as > > X2 is a different 32768 kHz crystal. > > Thanks for your patch! > > > Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> > > This is not what I suggested. > The bindings should document the meaning of the clock indices. OK, will add this meaning in description. > > > Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock > > generator bindings") > > This patch is not a critical fix. Will remove it in next version. Cheers, Biju
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml index 839648e753d4..8260af2a36db 100644 --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml @@ -68,7 +68,7 @@ examples: reg = <0x68>; #clock-cells = <1>; - clocks = <&x1_x2>; + clocks = <&x1>; renesas,settings = [ 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf @@ -79,8 +79,8 @@ examples: assigned-clocks = <&versa3 0>, <&versa3 1>, <&versa3 2>, <&versa3 3>, <&versa3 4>, <&versa3 5>; - assigned-clock-rates = <12288000>, <25000000>, - <12000000>, <11289600>, - <11289600>, <24000000>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; }; };
Fix the "assigned-clock-rates" for each clock output in the example based on Table 3. ("Output Source") in the 5P35023 datasheet(ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}). While at it, replace clocks phandle in the example from x1_x2->x1 as X2 is a different 32768 kHz crystal. Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock generator bindings") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- v3->v4: * Dropped clock-output-names as there is no validation for it and people can get it wrong. * Updated commit header, description and example to reflect this change * Retained Ack tag from Conor and Krzysztof as it is trivial change. v2->v3: * No change. v1->v2: * Updated commit description to make it clear it fixes "assigned-clock-rates" in the example based on 5P35023 datasheet. --- .../devicetree/bindings/clock/renesas,5p35023.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)