Message ID | 20230913203805.465780-1-ralph.siemsen@linaro.org (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | [v2,1/2] clk: renesas: r9a06g032: fix kerneldoc warning | expand |
Hi Ralph, ralph.siemsen@linaro.org wrote on Wed, 13 Sep 2023 16:38:04 -0400: > Mention the 'dual' structure in the kdoc. This fixes the following > W=1 warning during build: > > > drivers/clk/renesas/r9a06g032-clocks.c:119: warning: Function parameter or member 'dual' not described in 'r9a06g032_clkdesc' > > Reported-by: kernel test robot <lkp@intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202309101314.kTRoxND5-lkp@intel.com/ > Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Thanks, Miquèl
On Wed, Sep 13, 2023 at 10:38 PM Ralph Siemsen <ralph.siemsen@linaro.org> wrote: > Mention the 'dual' structure in the kdoc. This fixes the following > W=1 warning during build: > > > drivers/clk/renesas/r9a06g032-clocks.c:119: warning: Function parameter or member 'dual' not described in 'r9a06g032_clkdesc' > > Reported-by: kernel test robot <lkp@intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202309101314.kTRoxND5-lkp@intel.com/ > Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> > --- > Changes in v2: > - split the warning fix into separate commit Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v6.7. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 55db63c7041a..aa00543fe865 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -109,6 +109,7 @@ enum gate_type { * must be in ascending order, zero for unused * @div: divisor for fixed-factor clock * @mul: multiplier for fixed-factor clock + * @dual: substructure for dual clock gates * @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7 * @sel: select either g1/r1 or g2/r2 as clock source * @g1: 1st source gate (clock enable/disable)