From patchwork Mon Oct 9 09:37:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13413238 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C797AE95A8E for ; Mon, 9 Oct 2023 09:39:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345928AbjJIJjx (ORCPT ); Mon, 9 Oct 2023 05:39:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345996AbjJIJjv (ORCPT ); Mon, 9 Oct 2023 05:39:51 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ECBD94; Mon, 9 Oct 2023 02:39:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696844389; x=1728380389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IFHxvV76DQ6UmIeCUgXcZ1c22Kaa/5MKcYvW0mJV6W4=; b=ytNFsULQkAtxILLizPjB0iH8+1ZLeYWGnituqPePK+vObDUPPNnmx/Fo 1OoP9chQkrNd4nJBtHd0jxQ4ILF8G2KkaBL5G8Z2y4SIcN0eVnPJYlGYr 4GR/u9NLE1a6LFLT4oe8RyK7Ls2VtnE1tSZFqyGxssu5fFoLbS42w3qZh /TQbPRB8puYrOGYYmSPooy5BhvqjiN2EOs83bvEPQbT0cG/QO650yhU7u 6Xhh6VraQs0TQ+0nAATfOs9SWYShcSy1gBWXBZP3038JtK+DG5jr/wkGj m9HQVSYZGpsF4hbkUttX9H4JeMrXraUxCiRMKwQ+Q5mRr6cvGIFGj+cS0 w==; X-CSE-ConnectionGUID: ss/kXsifRKO4Oj8Q887AdA== X-CSE-MsgGUID: Npy1MPcYTa+Nx9vgamJKCQ== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="9216030" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Oct 2023 02:39:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:39:47 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:39:43 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:45 +0100 Message-ID: <20231009-rockfish-wistful-3e0106be968c@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2237; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=IFHxvV76DQ6UmIeCUgXcZ1c22Kaa/5MKcYvW0mJV6W4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ1/udH4lYKXuf7K3PXt9hU+nK5Ps4f+8GzyeMSVuuFD5 ePK6jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExEyZaRYfZrtus/Es92XF/zJnGLa/ mU1NMNFeGn9/adOlukJx/bNJ2RYY1cNOfG6T/efnnT8dxvfnjXQmevbBnXI0mGN0yC7nt+4AAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..a6faf24f1dba 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -22,6 +22,9 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -48,6 +51,9 @@ cpu1: cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -76,6 +82,9 @@ cpu2: cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -104,6 +113,9 @@ cpu3: cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -132,6 +144,9 @@ cpu4: cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;