@@ -1997,6 +1997,21 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
return 0;
}
+static int spi_nor_generic_post_sfdp_fixup(struct spi_nor *nor)
+{
+ struct spi_device *spi = nor->spimem->spi;
+ const u8 *id = nor->id;
+
+ if (spi->mode & SPI_TX_QUAD && nor->spimem) {
+ const struct spi_nor_id *at25ql128a_id = SNOR_ID(0x1f, 0x42, 0x18);
+
+ if (!memcmp(id, at25ql128a_id->bytes, at25ql128a_id->len))
+ return spi_mem_set_iofv(nor->spimem, 0xff);
+ }
+
+ return 0;
+}
+
static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_atmel,
&spi_nor_eon,
@@ -2015,8 +2030,13 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_xmc,
};
+static const struct spi_nor_fixups spi_nor_generic_fixups = {
+ .post_sfdp = spi_nor_generic_post_sfdp_fixup,
+};
+
static const struct flash_info spi_nor_generic_flash = {
.name = "spi-nor-generic",
+ .fixups = &spi_nor_generic_fixups,
};
static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
Some generic flash devices such as Renesas AT25QL128A serial nor flash requires the IO pins must be in high-impedance before the falling edge of the first data out clock for the Fast Read Quad IO. Add post_sfdp() callback for generic flash devices and then call spi_mem_set_iofv() to configure IO fixed value to control the pin state. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/mtd/spi-nor/core.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)