diff mbox series

[v4,03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller

Message ID 20231122121235.827122-4-peterlin@andestech.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Support Andes PMU extension | expand

Commit Message

Yu-Chien Peter Lin Nov. 22, 2023, 12:12 p.m. UTC 
Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located.

To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, we add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as private data.

Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node.
e.g.,

  cpu0: cpu@0 {
      compatible = "andestech,ax45mp", "riscv";
      ...
      cpu0-intc: interrupt-controller {
          #interrupt-cells = <0x01>;
          compatible = "andestech,cpu-intc", "riscv,cpu-intc";
          interrupt-controller;
      };
  };

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - Return -ENXIO if no valid compatible INTC found
  - Allow falling back to generic RISC-V INTC
Changes v3 -> v4: (Suggested by Thomas [1])
  - Add comment to andes irq chip function
  - Refine code flow to share with generic RISC-V INTC and ACPI
  - Move Andes specific definitions to include/linux/soc/andes/irq.h  

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
---
 drivers/irqchip/irq-riscv-intc.c | 51 ++++++++++++++++++++++++++++----
 include/linux/soc/andes/irq.h    | 17 +++++++++++
 2 files changed, 63 insertions(+), 5 deletions(-)
 create mode 100644 include/linux/soc/andes/irq.h

Comments

Thomas Gleixner Dec. 8, 2023, 4:01 p.m. UTC | #1 
On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, we add a chip parameter to riscv_intc_init_common(), so it can be

s/we//

See: Documentation/process/

> passed to the irq_domain_set_info() as private data.
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index 2fdd40f2a791..30f0036c8978 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -17,6 +17,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/smp.h>
> +#include <linux/soc/andes/irq.h>
>  
>  static struct irq_domain *intc_domain;
>  
> @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
>  	csr_set(CSR_IE, BIT(d->hwirq));
>  }
>  
> +static void andes_intc_irq_mask(struct irq_data *d)
> +{
> +	/*
> +	 * Andes specific S-mode local interrupt causes (hwirq)
> +	 * are defined as (256 + n) and controlled by n-th bit
> +	 * of SLIE.
> +	 */
> +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);

How is this supposed to be correct with BITS_PER_LONG == 64?

> +
> +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> +		csr_clear(CSR_IE, mask);
> +	else
> +		csr_clear(ANDES_CSR_SLIE, mask);
> +}
> +
> +static void andes_intc_irq_unmask(struct irq_data *d)
> +{
> +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);

Ditto.

> +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> +		csr_set(CSR_IE, mask);
> +	else
> +		csr_set(ANDES_CSR_SLIE, mask);
> +}

>  static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
>  				 irq_hw_number_t hwirq)
>  {
> +	struct irq_chip *chip = d->host_data;
> +
>  	irq_set_percpu_devid(irq);
> -	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
> +	irq_domain_set_info(d, irq, hwirq, chip, d->host_data,

So this sets 'chip_data' to the chip itself. What's the point? Just set
it to NULL as the chip obviously does not need chip_data at all.

>  			    handle_percpu_devid_irq, NULL, NULL);
>  
>  	return 0;
> @@ -112,11 +147,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
>  	return intc_domain->fwnode;
>  }
>  
> -static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> +static int __init riscv_intc_init_common(struct fwnode_handle *fn,
> +					 struct irq_chip *chip)
>  {
>  	int rc;
>  
> -	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
> +	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
>  	if (!intc_domain) {
>  		pr_err("unable to add IRQ domain\n");
>  		return -ENXIO;
> @@ -138,6 +174,7 @@ static int __init riscv_intc_init(struct device_node *node,
>  {
>  	int rc;
>  	unsigned long hartid;
> +	struct irq_chip *chip = &riscv_intc_chip;

https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-declarations

Thanks

        tglx
Yu-Chien Peter Lin Dec. 12, 2023, 10:28 a.m. UTC | #2 
Hi Thomas,

On Fri, Dec 08, 2023 at 05:01:36PM +0100, Thomas Gleixner wrote:
> On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> > To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> > ACPI, we add a chip parameter to riscv_intc_init_common(), so it can be
> 
> s/we//
> 
> See: Documentation/process/
> 
> > passed to the irq_domain_set_info() as private data.
> > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > index 2fdd40f2a791..30f0036c8978 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -17,6 +17,7 @@
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> >  #include <linux/smp.h>
> > +#include <linux/soc/andes/irq.h>
> >  
> >  static struct irq_domain *intc_domain;
> >  
> > @@ -46,6 +47,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
> >  	csr_set(CSR_IE, BIT(d->hwirq));
> >  }
> >  
> > +static void andes_intc_irq_mask(struct irq_data *d)
> > +{
> > +	/*
> > +	 * Andes specific S-mode local interrupt causes (hwirq)
> > +	 * are defined as (256 + n) and controlled by n-th bit
> > +	 * of SLIE.
> > +	 */
> > +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> 
> How is this supposed to be correct with BITS_PER_LONG == 64?

Yes, I should subtract ANDES_SLI_CAUSE_BASE directly here.

> > +
> > +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > +		csr_clear(CSR_IE, mask);
> > +	else
> > +		csr_clear(ANDES_CSR_SLIE, mask);
> > +}
> > +
> > +static void andes_intc_irq_unmask(struct irq_data *d)
> > +{
> > +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> 
> Ditto.
> 
> > +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > +		csr_set(CSR_IE, mask);
> > +	else
> > +		csr_set(ANDES_CSR_SLIE, mask);
> > +}
> 
> >  static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
> >  				 irq_hw_number_t hwirq)
> >  {
> > +	struct irq_chip *chip = d->host_data;
> > +
> >  	irq_set_percpu_devid(irq);
> > -	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
> > +	irq_domain_set_info(d, irq, hwirq, chip, d->host_data,
> 
> So this sets 'chip_data' to the chip itself. What's the point? Just set
> it to NULL as the chip obviously does not need chip_data at all.

Will fix. Thanks.

Best regards,
Peter Lin

> >  			    handle_percpu_devid_irq, NULL, NULL);
> >  
> >  	return 0;
> > @@ -112,11 +147,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
> >  	return intc_domain->fwnode;
> >  }
> >  
> > -static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> > +static int __init riscv_intc_init_common(struct fwnode_handle *fn,
> > +					 struct irq_chip *chip)
> >  {
> >  	int rc;
> >  
> > -	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
> > +	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
> >  	if (!intc_domain) {
> >  		pr_err("unable to add IRQ domain\n");
> >  		return -ENXIO;
> > @@ -138,6 +174,7 @@ static int __init riscv_intc_init(struct device_node *node,
> >  {
> >  	int rc;
> >  	unsigned long hartid;
> > +	struct irq_chip *chip = &riscv_intc_chip;
> 
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-declarations
> 
> Thanks
> 
>         tglx
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 2fdd40f2a791..30f0036c8978 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -17,6 +17,7 @@ 
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/smp.h>
+#include <linux/soc/andes/irq.h>
 
 static struct irq_domain *intc_domain;
 
@@ -46,6 +47,31 @@  static void riscv_intc_irq_unmask(struct irq_data *d)
 	csr_set(CSR_IE, BIT(d->hwirq));
 }
 
+static void andes_intc_irq_mask(struct irq_data *d)
+{
+	/*
+	 * Andes specific S-mode local interrupt causes (hwirq)
+	 * are defined as (256 + n) and controlled by n-th bit
+	 * of SLIE.
+	 */
+	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+		csr_clear(CSR_IE, mask);
+	else
+		csr_clear(ANDES_CSR_SLIE, mask);
+}
+
+static void andes_intc_irq_unmask(struct irq_data *d)
+{
+	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+		csr_set(CSR_IE, mask);
+	else
+		csr_set(ANDES_CSR_SLIE, mask);
+}
+
 static void riscv_intc_irq_eoi(struct irq_data *d)
 {
 	/*
@@ -69,11 +95,20 @@  static struct irq_chip riscv_intc_chip = {
 	.irq_eoi = riscv_intc_irq_eoi,
 };
 
+static struct irq_chip andes_intc_chip = {
+	.name       = "RISC-V INTC",
+	.irq_mask   = andes_intc_irq_mask,
+	.irq_unmask = andes_intc_irq_unmask,
+	.irq_eoi    = riscv_intc_irq_eoi,
+};
+
 static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
 				 irq_hw_number_t hwirq)
 {
+	struct irq_chip *chip = d->host_data;
+
 	irq_set_percpu_devid(irq);
-	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
+	irq_domain_set_info(d, irq, hwirq, chip, d->host_data,
 			    handle_percpu_devid_irq, NULL, NULL);
 
 	return 0;
@@ -112,11 +147,12 @@  static struct fwnode_handle *riscv_intc_hwnode(void)
 	return intc_domain->fwnode;
 }
 
-static int __init riscv_intc_init_common(struct fwnode_handle *fn)
+static int __init riscv_intc_init_common(struct fwnode_handle *fn,
+					 struct irq_chip *chip)
 {
 	int rc;
 
-	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
+	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
@@ -138,6 +174,7 @@  static int __init riscv_intc_init(struct device_node *node,
 {
 	int rc;
 	unsigned long hartid;
+	struct irq_chip *chip = &riscv_intc_chip;
 
 	rc = riscv_of_parent_hartid(node, &hartid);
 	if (rc < 0) {
@@ -162,10 +199,14 @@  static int __init riscv_intc_init(struct device_node *node,
 		return 0;
 	}
 
-	return riscv_intc_init_common(of_node_to_fwnode(node));
+	if (of_device_is_compatible(node, "andestech,cpu-intc"))
+		chip = &andes_intc_chip;
+
+	return riscv_intc_init_common(of_node_to_fwnode(node), chip);
 }
 
 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
 
 #ifdef CONFIG_ACPI
 
@@ -192,7 +233,7 @@  static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
 		return -ENOMEM;
 	}
 
-	return riscv_intc_init_common(fn);
+	return riscv_intc_init_common(fn, &riscv_intc_chip);
 }
 
 IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
new file mode 100644
index 000000000000..f03e68fea261
--- /dev/null
+++ b/include/linux/soc/andes/irq.h
@@ -0,0 +1,17 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __ANDES_IRQ_H
+#define __ANDES_IRQ_H
+
+/* Andes PMU irq number */
+#define ANDES_RV_IRQ_PMU		18
+#define ANDES_SLI_CAUSE_BASE		256
+
+/* Andes PMU related registers */
+#define ANDES_CSR_SLIE			0x9c4
+#define ANDES_CSR_SLIP			0x9c5
+#define ANDES_CSR_SCOUNTEROF		0x9d4
+
+#endif /* __ANDES_IRQ_H */