From patchwork Tue Nov 28 19:56:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13471676 X-Patchwork-Delegate: geert@linux-m68k.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HGcnp9tV" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E46110F0; Tue, 28 Nov 2023 12:08:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701202081; x=1732738081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CyMweha2ZvuLisSoPmNJvwBvM8UVF+24ES7V+e13w7A=; b=HGcnp9tV83iHVtaN4q3xBFp0xWEVUhCfIt65jQiQKYMnqYLsLBsWoHnP +utQEqDPyVspjj5ttLpu5gQW7WdHIAL4x8SurKAMCA97rnfGJbMa4rSLm B74VPX/fV4fBEgskWaVvAxn9qumO7tJad1A5GcTe25Z4OyRQc/BEVU0hQ z1NM464wnJSNVU9ChrJB+Ke71cvKOipy3ezNJFylUCgOhkdGETRg8rNvE rX89URAPImuobIdRzJ5zHbgCmx/GJBv0sLaj1+gy940VFseo7VTA3WOpU Mr2ZNO752ImjTBdnNyWD31xTzSbNEKqC5Sn4cjJMhXRnT+U/KsUT4jko+ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="457346999" X-IronPort-AV: E=Sophos;i="6.04,234,1695711600"; d="scan'208";a="457346999" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 12:06:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="1100254115" X-IronPort-AV: E=Sophos;i="6.04,234,1695711600"; d="scan'208";a="1100254115" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga005.fm.intel.com with ESMTP; 28 Nov 2023 12:02:18 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 4F6ADA96; Tue, 28 Nov 2023 22:01:58 +0200 (EET) From: Andy Shevchenko To: Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Rasmus Villemoes , =?utf-8?q?Jonathan_Neusch?= =?utf-8?q?=C3=A4fer?= , Krzysztof Kozlowski , =?utf-8?q?Uwe_Kleine-?= =?utf-8?q?K=C3=B6nig?= , Geert Uytterhoeven , Biju Das , Claudiu Beznea , Jianlong Huang , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, openbmc@lists.ozlabs.org, linux-mips@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Ray Jui , Scott Branden , Broadcom internal kernel review list , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , Pengutronix Kernel Team , Sascha Hauer , NXP Linux Team , Sean Wang , Paul Cercueil , Lakshmi Sowjanya D , Andy Gross , Bjorn Andersson , Konrad Dybcio , Emil Renner Berthing , Hal Feng Subject: [PATCH v3 09/22] pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP() Date: Tue, 28 Nov 2023 21:56:58 +0200 Message-ID: <20231128200155.438722-10-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com> References: <20231128200155.438722-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro. Utilize them instead of open coded variants in the driver. Reviewed-by: Jonathan Neuschäfer Signed-off-by: Andy Shevchenko --- drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 0cff44b07b29..4589900244c7 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -474,9 +474,8 @@ enum { #undef WPCM450_GRP }; -static struct group_desc wpcm450_groups[] = { -#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \ - .num_pins = ARRAY_SIZE(x ## _pins) } +static struct pingroup wpcm450_groups[] = { +#define WPCM450_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins)) WPCM450_GRPS #undef WPCM450_GRP }; @@ -852,7 +851,7 @@ static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev, const unsigned int **pins, unsigned int *npins) { - *npins = wpcm450_groups[selector].num_pins; + *npins = wpcm450_groups[selector].npins; *pins = wpcm450_groups[selector].pins; return 0; @@ -901,7 +900,7 @@ static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev, struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins, - wpcm450_groups[group].num_pins, function); + wpcm450_groups[group].npins, function); return 0; }