From patchwork Wed Dec 13 07:02:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13490469 X-Patchwork-Delegate: geert@linux-m68k.org Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEA2A13D; Tue, 12 Dec 2023 23:05:48 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BD74IhD032637; Wed, 13 Dec 2023 15:04:18 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Dec 2023 15:04:14 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Date: Wed, 13 Dec 2023 15:02:59 +0800 Message-ID: <20231213070301.1684751-15-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com> References: <20231213070301.1684751-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BD74IhD032637 xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ba4d2c673ac8..2dad2b22824a 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -22,7 +22,7 @@ c910_0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -46,7 +46,7 @@ c910_1: cpu@1 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -70,7 +70,7 @@ c910_2: cpu@2 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -94,7 +94,7 @@ c910_3: cpu@3 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;