From patchwork Mon Feb 12 11:37:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13552970 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E18824B57 for ; Mon, 12 Feb 2024 11:37:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737849; cv=none; b=ct5DI28fY4RVWtBBFM2vPU16z0K24fr5tfZ6tzH9CsPdmYXMeVgkzDUsHPYXfDPNU/79KO96ysWULzN38OMsnX/KO739WekhSfhy4gAE5wxWmNlLZfV0uv7RmjnuA499uUGQPyZ6YBqAhKzwlkiNYTPcJhquYIBO5j8IVZvznwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737849; c=relaxed/simple; bh=RIVxkBsMCAi17kQFjBPikwksQcnIJ9vrtIR7V3mK8U4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FDnFRUAwCdEWFWMpR91jXkmxUjovFV+S5Ob+3OaiRmW/gGZrLM8OinsOvbydOVpDA32iN2fO1sHzf8WtaVtMt3fTHozY8Xu7UDlO4hK7LCLndrXeJ6kgkDuAx1Em2dkutNiMEAP87Q2oCtxEIIMfKGxE/k9HUApGROntxA89hhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.05,263,1701097200"; d="scan'208";a="193656664" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 12 Feb 2024 20:37:20 +0900 Received: from localhost.localdomain (unknown [10.226.92.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4874641A9A9B; Mon, 12 Feb 2024 20:37:18 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Lad Prabhakar , Marc Zyngier , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/5] irqchip/renesas-rzg2l: Prevent IRQ HW race Date: Mon, 12 Feb 2024 11:37:08 +0000 Message-Id: <20240212113712.71878-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> References: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As per section "8.8.2 Clear Timing of Interrupt Cause" of the RZ/G2L hardware manual (Rev.1.45 Jan, 2024), it is mentioned that we need to clear the interrupt cause flag in the isr. It takes some time for the cpu to clear the interrupt cause flag. Therefore, to prevent another occurrence of interrupt due to this delay, the interrupt cause flag is read after clearing. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 9494fc26259c..46f9b07e0e8a 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -111,8 +111,11 @@ static void rzg2l_tint_eoi(struct irq_data *d) u32 reg; reg = readl_relaxed(priv->base + TSCR); - if (reg & bit) + if (reg & bit) { writel_relaxed(reg & ~bit, priv->base + TSCR); + /* Read to avoid irq generation due to irq clearing delay */ + readl_relaxed(priv->base + TSCR); + } } static void rzg2l_irqc_eoi(struct irq_data *d)