| Message ID | 20240214052144.1966569-1-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Under Review |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: r8a779f0: Add GICv3 ITS | expand |
Hi Shimoda-san, Thanks for your patch! On Wed, Feb 14, 2024 at 6:21 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > This SoC has GICv3 ITS and PCIe host mode on this SoC can use it. > So, add GIC ITS node into GIC node and update interrupt-map in PCIe node. > > Note that PCIe nodes need msi-parent property to use the ITS for MSI. > However, it requires PCIe driver's update. Especially, vendor-specific > registers' setting is needed. So, this patch doesn't add msi-parent > properties into PCIe nodes. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Is there any value in adding the GICv3 ITS node now, without msi-parent properties pointing to it? I.e. does applying this patch enable extra functionality yet? > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > @@ -1262,11 +1262,19 @@ ipmmu_mm: iommu@eefc0000 { > gic: interrupt-controller@f1000000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>; > - #address-cells = <0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > interrupt-controller; > reg = <0x0 0xf1000000 0 0x20000>, > <0x0 0xf1060000 0 0x110000>; > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic_its: msi-controller@f1040000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x0 0xf1040000 0 0x20000>; > + msi-controller; Missing "#msi-cells = <1>", which is a required property. > + }; > }; > > prr: chipid@fff00044 { The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 72cf30341fc4..63c14ef072b9 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -778,10 +778,10 @@ pciec0: pcie@e65d0000 { dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; }; @@ -815,10 +815,10 @@ pciec1: pcie@e65d8000 { dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; }; @@ -1262,11 +1262,19 @@ ipmmu_mm: iommu@eefc0000 { gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; - #address-cells = <0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: msi-controller@f1040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xf1040000 0 0x20000>; + msi-controller; + }; }; prr: chipid@fff00044 {
This SoC has GICv3 ITS and PCIe host mode on this SoC can use it. So, add GIC ITS node into GIC node and update interrupt-map in PCIe node. Note that PCIe nodes need msi-parent property to use the ITS for MSI. However, it requires PCIe driver's update. Especially, vendor-specific registers' setting is needed. So, this patch doesn't add msi-parent properties into PCIe nodes. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 26 +++++++++++++++-------- 1 file changed, 17 insertions(+), 9 deletions(-)