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AJvYcCVKYznC4rULt5G1Xky2gQbZwDctwjxHVvYY23DqoiA7+ofmeRiaW449AjfvFL9fi7lFWm9kue2sqzHroMkjYc57X4eDrMqoenyZ4TVCSZngvianKWkyiK19PaVbajo4IDU9X3qYqYISkdJfYctMruuGINAxXzckcg2Hqp6Sb6R0BJpzUNZpXpRiZZsP X-Gm-Message-State: AOJu0YzpPK7bz02w11TLPD0+LHpvE1Kw2LIt7t5eUkwf0IzUWZfbITRH c5Jc+0D6XvaZIdggFmTbAR5bw+qatD62kQBmigiOety3D/+7GV/XGSaTTi/Q X-Google-Smtp-Source: AGHT+IGwHO1+9bzW+aeUsfuP4YK/bsb8fDl3AXVY3KJdwWdOV6wi0ZHETgfjh87YtN31Ug3+vIUc7g== X-Received: by 2002:a05:600c:1396:b0:411:d889:f3cd with SMTP id u22-20020a05600c139600b00411d889f3cdmr8958674wmf.34.1708358993362; Mon, 19 Feb 2024 08:09:53 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:3c2e:cd45:f50f:f083]) by smtp.gmail.com with ESMTPSA id l14-20020a7bc44e000000b00411d1ce4f9dsm11592670wmi.34.2024.02.19.08.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 08:09:52 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Date: Mon, 19 Feb 2024 16:09:10 +0000 Message-Id: <20240219160912.1206647-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219160912.1206647-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240219160912.1206647-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add DT binding documentation for System Controller (SYS) found on RZ/V2H{P} ("R9A09G057") SoC's. SYS block contains the SYS_LSI_DEVID register which can be used to retrieve SoC version information. Signed-off-by: Lad Prabhakar Reviewed-by: Fabrizio Castro --- Note, the reset index in example node will be update once the CPG support is upstreamed. --- .../soc/renesas/renesas,r9a09g057-sys.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml new file mode 100644 index 000000000000..ba30d7734ee8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H{P} System Controller (SYS) + +maintainers: + - Geert Uytterhoeven + +description: + The RZ/V2H{P} SYS (System Controller) controls the overall + configuration of the LSI and supports the following functions, + - Trust zone control + - Extend access by specific masters to address beyond 4GB space + - GBETH configuration + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU + - LSI version + - WDT stop control + - General registers + +properties: + compatible: + const: renesas,r9a09g057-sys + + reg: + maxItems: 1 + + clocks: + items: + - description: Clock from external oscillator + + resets: + items: + - description: SYS_0_PRESETN reset signal + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + sys: system-controller@10430000 { + compatible = "renesas,r9a09g057-sys"; + reg = <0x10430000 0x10000>; + clocks = <&extal_clk>; + resets = <&cpg 1>; + };