From patchwork Tue Feb 20 19:43:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13564437 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5DA521474A8; Tue, 20 Feb 2024 19:43:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708458225; cv=none; b=ka9rGYOg1hKtEtHNu2peDIvXyI0eOyDwOyLZko6vHWgu1faMsqDx5lw/koX1p8hmooxFpYJ3sSxgKIopRTwyWz0uIHMtVzPjzgjTHoOtzvJXU7es3Bg8rRMFtauGMDUaSLI8ptltM54kXwX5bv9yNWfct6tf1gC5TkKkFRCNTxI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708458225; c=relaxed/simple; bh=3vr/BylHpXBS7rL/y9/mGwL07CaqDpFte7jacl3IzYI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IwBsLe5JamfS8ZnkapqoUnzomHS482xB7mQIOITNMNApPAcftrZ+Oar2XJ6OrFB6jWSHIHfXmMWbdRb2zrD1bJHlZ+HSTNv2kBnzpVdI0OOQaYDmoXSii8hJczRWEAsXwXSiLVwZOHLiOX9ObNOjFiOMAxfCtaEFwX8OhcwCj80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,174,1705330800"; d="scan'208";a="194620723" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 21 Feb 2024 04:43:36 +0900 Received: from localhost.localdomain (unknown [10.226.92.246]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A1EF440031D1; Wed, 21 Feb 2024 04:43:31 +0900 (JST) From: Biju Das To: Thierry Reding , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , Fabrizio Castro , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Rob Herring Subject: [PATCH v18 2/4] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Date: Tue, 20 Feb 2024 19:43:16 +0000 Message-Id: <20240220194318.672443-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240220194318.672443-1-biju.das.jz@bp.renesas.com> References: <20240220194318.672443-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 RZ/G2L GPT IP supports output pin disable function by dead time error and detecting short-circuits between output pins. Add documentation for the optional property renesas,poegs to link a pair of GPT IOs with POEG. Signed-off-by: Biju Das Reviewed-by: Rob Herring --- v17->v18: * No change. v16->v17: * No change. v15->v16: * No change. v14->v15: * No change. v3->v14: * Add Rb tag from Rob. * Moved the patch from series[1] to here. [1] https://lore.kernel.org/linux-renesas-soc/20221215205843.4074504-1-biju.das.jz@bp.renesas.com/T/#t v2->v3: * Moved minItems/MaxItems one level up. v1->v2: * removed quotes from ref * Added maxItems and minItems for renesas,poegs property * Added enums for gpt index --- .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml index d9374144d82d..957cf28b2c4c 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml @@ -245,6 +245,28 @@ properties: resets: maxItems: 1 + renesas,poegs: + minItems: 1 + maxItems: 8 + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to POEG instance that serves the output disable + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ] + description: | + An index identifying pair of GPT channels. + <0> : GPT channels 0 and 1 + <1> : GPT channels 2 and 3 + <2> : GPT channels 4 and 5 + <3> : GPT channels 6 and 7 + <4> : GPT channels 8 and 9 + <5> : GPT channels 10 and 11 + <6> : GPT channels 12 and 13 + <7> : GPT channels 14 and 15 + description: + A list of phandle and channel index pair tuples to the POEGs that handle the + output disable for the GPT channels. + required: - compatible - reg @@ -375,4 +397,5 @@ examples: power-domains = <&cpg>; resets = <&cpg R9A07G044_GPT_RST_C>; #pwm-cells = <2>; + renesas,poegs = <&poeggd 4>; };