From patchwork Tue Mar 5 18:39:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13582842 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B10A41426F for ; Tue, 5 Mar 2024 18:39:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663981; cv=none; b=qpw6nN+6U/anGwvLJGECFDkl0Adef+bvxIMK7+nJ4BjU4rKzkQHHSTbyhJPGEAeYH28RL1e2rVFRYabd5Jxudp4R/r3H7ndZtBR/CJhLQfqKHeVgsnqIfvOCUZVLk1kkWJLFwgxr5hiAaYFhjEI+Nz6Tzbp5Lcbw/ykL8uFGzy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663981; c=relaxed/simple; bh=2Pr8PMAMW8RrhjX5cQ4ZX7nTzQ+0t0yWSvhfMDCrQD8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a9HdThu9xjn27NZKpSaXBxEJasf0FAFT5j3xZ08OVCEeL9Toa76fOtYDpUnxtUTFcGobmIUnH5iAm7bUfyJTq1qDuskaDjO15lKs5hM/V+MyybtIHcnwUOsRXKw6I37WcF8069gm+PfWxsMtcqFolP+tJ5YsD3o/dLv2u+2an9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,206,1705330800"; d="scan'208";a="200436912" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2024 03:39:39 +0900 Received: from localhost.localdomain (unknown [10.226.92.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 578774003ED1; Wed, 6 Mar 2024 03:39:37 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Marc Zyngier , Lad Prabhakar , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/5] irqchip/renesas-rzg2l: Fix spurious IRQ Date: Tue, 5 Mar 2024 18:39:21 +0000 Message-Id: <20240305183922.138727-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> References: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G2L interrupt chip, interrupt masking is required before changing the NMI, IRQ, TINT interrupt settings. Apart from this, after setting the edge type it is required to clear interrupt status register in order to avoid spurious IRQ. For IRQ edge type, use raw_spin_lock()->raw_spin_lock_irqsave() and in case of TINT edge type use TIEN for interrupt masking. Then set the interrupt detection register followed by clearing interrupt status register to fix the spurious IRQ. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das --- v1->v2: * Updated commit header and description. * Extended spurious IRQ fix to IRQ as well. * Updated the logic for rzg2l_disable_tint_and_set_tint_source() and rzg2l_tint_set_edge(). --- drivers/irqchip/irq-renesas-rzg2l.c | 41 ++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 8133f05590b6..e793b8f07dac 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -181,8 +181,11 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hwirq = irqd_to_hwirq(d); + u32 iitseln = hwirq - IRQC_IRQ_START; + bool clear_irq_int = false; + unsigned long flags; u16 sense, tmp; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -192,37 +195,59 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_FALLING: sense = IITSR_IITSEL_EDGE_FALLING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_RISING: sense = IITSR_IITSEL_EDGE_RISING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_BOTH: sense = IITSR_IITSEL_EDGE_BOTH; + clear_irq_int = true; break; default: return -EINVAL; } - raw_spin_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, flags); tmp = readl_relaxed(priv->base + IITSR); - tmp &= ~IITSR_IITSEL_MASK(hw_irq); - tmp |= IITSR_IITSEL(hw_irq, sense); + tmp &= ~IITSR_IITSEL_MASK(iitseln); + tmp |= IITSR_IITSEL(iitseln, sense); + if (clear_irq_int) + rzg2l_clear_irq_int(priv, hwirq); writel_relaxed(tmp, priv->base + IITSR); - raw_spin_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, flags); return 0; } +static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv, + u32 reg, u32 tssr_offset, u8 tssr_index) +{ + u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); + u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset)); + + /* Clear the relevant byte in reg */ + reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); + /* Set TINT and leave TIEN clear */ + reg |= tint << TSSEL_SHIFT(tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + + return reg | tien; +} + static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; + u32 tssr_offset = TSSR_OFFSET(titseln); + u8 tssr_index = TSSR_INDEX(titseln); u8 index, sense; - u32 reg; + u32 reg, tssr; switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -244,10 +269,14 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) } raw_spin_lock(&priv->lock); + tssr = readl_relaxed(priv->base + TSSR(tssr_index)); + tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index); reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); writel_relaxed(reg, priv->base + TITSR(index)); + rzg2l_clear_tint_int(priv, hwirq); + writel_relaxed(tssr, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); return 0;