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([82.78.167.38]) by smtp.gmail.com with ESMTPSA id v23-20020a1709067d9700b00a42ee62b634sm8200648ejo.106.2024.03.07.06.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Mar 2024 06:07:55 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 07/10] clk: renesas: r9a08g045: Add support for power domains Date: Thu, 7 Mar 2024 16:07:25 +0200 Message-Id: <20240307140728.190184-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240307140728.190184-1-claudiu.beznea.uj@bp.renesas.com> References: <20240307140728.190184-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Instantiate power domains for the currently enabled IPs of R9A08G045 SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Change in v2: - used DEF_REG_CONF() to describe register offests and bits - updated MSTOP bitmask for ddr domain - updated MSTOP config for oftde_ddr - kept the same description for gic as the CPG_BUS_ACPU_MSTOP register documentation in the latest HW manual version is wrong and it will be fixed; proper description for GIC is located in "Registers for Module Standby Mode" table - haven't added watchdog domain (was missing in v1, too, by mistake) as the watchdog restart handler will fail w/o patch [1]; with this pm domain support the watchdog will fail to probe; not sure what is the best option until [1] will be integrated [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240228083253.2640997-10-claudiu.beznea.uj@bp.renesas.com drivers/clk/renesas/r9a08g045-cpg.c | 61 +++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index c3e6da2de197..c64769082f5b 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -240,6 +240,62 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_DMAC_ACLK, }; +static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { + /* Keep always-on domain on the first position for proper domains registration. */ + DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, + DEF_REG_CONF(0, 0), + DEF_REG_CONF(0, 0), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("gic", R9A08G045_PD_GIC, + DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)), + DEF_REG_CONF(CPG_PWRDN_IP1, BIT(2)), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("ia55", R9A08G045_PD_IA55, + DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)), + DEF_REG_CONF(CPG_PWRDN_IP1, BIT(3)), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("dmac", R9A08G045_PD_DMAC, + DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)), + DEF_REG_CONF(0, 0), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("ddr", R9A08G045_PD_DDR, + DEF_REG_CONF(CPG_BUS_PERI_DDR_MSTOP, GENMASK(1, 0)), + DEF_REG_CONF(CPG_PWRDN_IP2, BIT(0)), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("tzcddr", R9A08G045_PD_TZCDDR, + DEF_REG_CONF(CPG_BUS_TZCDDR_MSTOP, GENMASK(2, 0)), + DEF_REG_CONF(CPG_PWRDN_IP2, BIT(1)), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("otfde_ddr", R9A08G045_PD_OTFDE_DDR, + DEF_REG_CONF(CPG_BUS_PERI_CPU2_MSTOP, BIT(2)), + DEF_REG_CONF(CPG_PWRDN_IP2, BIT(2)), + RZG2L_PD_F_ALWAYS_ON), + DEF_PD("sdhi0", R9A08G045_PD_SDHI0, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), + DEF_REG_CONF(CPG_PWRDN_IP1, BIT(13)), + RZG2L_PD_F_NONE), + DEF_PD("sdhi1", R9A08G045_PD_SDHI1, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), + DEF_REG_CONF(CPG_PWRDN_IP1, BIT(14)), + RZG2L_PD_F_NONE), + DEF_PD("sdhi2", R9A08G045_PD_SDHI2, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), + DEF_REG_CONF(CPG_PWRDN_IP1, BIT(15)), + RZG2L_PD_F_NONE), + DEF_PD("eth0", R9A08G045_PD_ETHER0, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), + DEF_REG_CONF(CPG_PWRDN_IP1, BIT(11)), + RZG2L_PD_F_NONE), + DEF_PD("eth1", R9A08G045_PD_ETHER1, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), + DEF_REG_CONF(CPG_PWRDN_IP1, BIT(12)), + RZG2L_PD_F_NONE), + DEF_PD("scif0", R9A08G045_PD_SCIF0, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), + DEF_REG_CONF(0, 0), + RZG2L_PD_F_NONE), +}; + const struct rzg2l_cpg_info r9a08g045_cpg_info = { /* Core Clocks */ .core_clks = r9a08g045_core_clks, @@ -260,5 +316,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = { .resets = r9a08g045_resets, .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ + /* Power domains */ + .pm_domains = r9a08g045_pm_domains, + .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains), + .pm_domain_pwrdn_mstop = true, + .has_clk_mon_regs = true, };