From patchwork Thu Mar 14 07:47:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13592177 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D965D2AEF5 for ; Thu, 14 Mar 2024 07:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710402524; cv=none; b=SWzJtNhgEa3d3cTfAIw0VTt1EAPaCg6xUeoJCv8Iq2WC0hsyeINrGsrx1zIGgfuSE1YXxPyYkqN6+5NtaohZbBo+qZNqBdJdXXS+hupVD66hrA87YE7UAR6BwXcuplaGJmn9AaDhLPutaLTOhEETuqIHEHXlB4oxxbK8dpkANBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710402524; c=relaxed/simple; bh=DDCZoLHduZCUgXgmwVWPg1p7qsh6fab55IAmfI5Ain8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C1s2Qne0SQltwqPg9BSK3UWP3TAK4iIntwXQ9N6TqyDsNjSeIHGBWjRbz+rBLpDVy2yJlcnsVZ6mWQt1YUK/BD2rbd1x5tcWRMO0hdbAxAJXishTEeAKgn7BrJRs8BCrk+EXp3GKbm2p/KV/uvEGlEfd2nhQmkxR6c4/uKOUGw0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ut3J0PG5; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ut3J0PG5" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1dd8dd198d0so4807615ad.3 for ; Thu, 14 Mar 2024 00:48:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710402521; x=1711007321; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ms4/cCoO9t4kQQ5ANCu4uj6Ldb1VzG42n8OC1+sLfgU=; b=ut3J0PG5aoL+1AP51/emA5y0khovFFhhyFUNdA6YRCcPqulVg3cMKGGqDWCEOQiyvw J29xINmFdZsaAuO2ewRp3+EAk6qrnTj/2+rC14rawYktcsCHkF/ipV1k0qfIfPIgWniD wWKPeVMhfjVCFU+aJ2eLivnM9FHtlDKV9Hn+5qM/3gK8PYZoPmoscV6eYdhyedhsB0/l rkB0jeGwKxQG4+vORTwVNF6GEpXW6XJPfdDWsa0OLDVf6grpRnkNwec3VWRBancPiaFH 2ybgAlSPHg66Lnzy72cDKNWIo1yURpLKWBlunpX0nj9eJyUjhyVU/EBUtXJdyzs9PMaL 8uDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710402521; x=1711007321; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ms4/cCoO9t4kQQ5ANCu4uj6Ldb1VzG42n8OC1+sLfgU=; b=gIOTlERI1g9Cp1FdupMd7AOZ1Oq6m4UTuruuLJhuY6WTpEkz0vrv4t3f4q+UEd1PbO vsd0q7wZpfjABXg10dXyoTBE9+AXoRSrmDmTPAWe9S6bg9VTcPXnbMv6KX7LWJiPVX1g flVqKc5LT+QcQTJlBTzKlBr1lZhrQOhxoRCBkOp6CZ6zvp2Q+u2+Vzrxdjft0KENuPd6 JQxaPnlnOu0OmxrAXgiH5hkwaKTnw/xKu58YmvDZE1qSJzfmfvmf1H+mrZnEx1CHxckb b8lYSVPTcGxEOnafx9ZIboDV6mRTUXo/6BJqHExFEj0G1YorTu98gxPjcXTi5fzHTdNC BTDg== X-Forwarded-Encrypted: i=1; AJvYcCWyrTmdgxqlrmr7shas/EdEhZpJV+ITn//Y6V+1Eznu5MlxQe5TMZNYlPWnzbRO8szCryEirM756I15yfh8CqmoVImmD+oytbdojmiDlj9VvOU= X-Gm-Message-State: AOJu0Yx/9cv+m7KXkVjDp4LgK3pA4eOaDIntENmH+7bA946QWzpL+LTA NU+m9I5OWYOXOsiemnewPn7hq9YMVitp5Oj247WemGnD5Tux6JnSXFC5L3mnDg== X-Google-Smtp-Source: AGHT+IE691S3aM4gKMiUgsGRIW3ULctLNBMnQ4nrhnhnHuQKKLPulBDD5SbY4N3axLN/JD7ImO6n6w== X-Received: by 2002:a17:902:b58c:b0:1dd:7e97:5054 with SMTP id a12-20020a170902b58c00b001dd7e975054mr1136947pls.50.1710402521088; Thu, 14 Mar 2024 00:48:41 -0700 (PDT) Received: from [127.0.1.1] ([117.207.30.211]) by smtp.gmail.com with ESMTPSA id l9-20020a170903120900b001dd4fabf695sm946321plh.38.2024.03.14.00.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 00:48:40 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 14 Mar 2024 13:17:59 +0530 Subject: [PATCH v10 1/8] PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240314-pci-dbi-rework-v10-1-14a45c5a938e@linaro.org> References: <20240314-pci-dbi-rework-v10-0-14a45c5a938e@linaro.org> In-Reply-To: <20240314-pci-dbi-rework-v10-0-14a45c5a938e@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Kishon Vijay Abraham I , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7480; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=DDCZoLHduZCUgXgmwVWPg1p7qsh6fab55IAmfI5Ain8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl8qvCnQdJMIv1bZzd098m/IpJQvgbGM7no+98q AfzVktaVcWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfKrwgAKCRBVnxHm/pHO 9VthB/9wT9n8vhm9l8pag5gd8e2pco5wnTqQ3KzAupDGg1zw/eHEvx+UhtRRgS+FzwG99b/RD+h oopWi0V2td1EIi4TYm4bxIWT42ldGsWRD73fYquq2D7V3bKVMssuNXVDQ6y4mz9sb0m+1yhuZlM hHEJ92AQoiRGfjSarKYYw1VL3f08n6XedMS+L9yyk3Hu8AcNhcBIi0+FdlbwZzoNqPpAQiv50cw C/BfRg+HFD5GaqyP/P0XLJzCExBmRAzOgv7NExvOFnlDEKGLswZNvUqYoWTeNt1uUX2YAl0Lyp7 lVhEtwVY+ZAA/3xo3+mChqFQfa4z4h8S5dvIkZq7eH27swQO X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 The DWC glue drivers requiring an active reference clock from the PCIe host for initializing their PCIe EP core, set a flag called 'core_init_notifier' to let DWC driver know that these drivers need a special attention during initialization. In these drivers, access to the hw registers (like DBI) before receiving the active refclk from host will result in access failure and also could cause a whole system hang. But the current DWC EP driver doesn't honor the requirements of the drivers setting 'core_init_notifier' flag and tries to access the DBI registers during dw_pcie_ep_init(). This causes the system hang for glue drivers such as Tegra194 and Qcom EP as they depend on refclk from host and have set the above mentioned flag. To workaround this issue, users of the affected platforms have to maintain the dependency with the PCIe host by booting the PCIe EP after host boot. But this won't provide a good user experience, since PCIe EP is _one_ of the features of those platforms and it doesn't make sense to delay the whole platform booting due to PCIe requiring active refclk. So to fix this issue, let's move all the DBI access from dw_pcie_ep_init() in the DWC EP driver to the dw_pcie_ep_init_complete() API. This API will only be called by the drivers setting 'core_init_notifier' flag once refclk is received from host. For the rest of the drivers that gets the refclk locally, this API will be called within dw_pcie_ep_init(). Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP mode") Co-developed-by: Vidya Sagar Signed-off-by: Vidya Sagar Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 120 ++++++++++++++---------- 1 file changed, 71 insertions(+), 49 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5befed2dc02b..c05304eabb89 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -602,11 +602,16 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct dw_pcie_ep_func *ep_func; + struct device *dev = pci->dev; + struct pci_epc *epc = ep->epc; unsigned int offset, ptm_cap_base; unsigned int nbars; u8 hdr_type; + u8 func_no; + int i, ret; + void *addr; u32 reg; - int i; hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) & PCI_HEADER_TYPE_MASK; @@ -617,6 +622,58 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) return -EIO; } + dw_pcie_version_detect(pci); + + dw_pcie_iatu_detect(pci); + + ret = dw_pcie_edma_detect(pci); + if (ret) + return ret; + + if (!ep->ib_window_map) { + ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows, + GFP_KERNEL); + if (!ep->ib_window_map) + goto err_remove_edma; + } + + if (!ep->ob_window_map) { + ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows, + GFP_KERNEL); + if (!ep->ob_window_map) + goto err_remove_edma; + } + + if (!ep->outbound_addr) { + addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), + GFP_KERNEL); + if (!addr) + goto err_remove_edma; + ep->outbound_addr = addr; + } + + for (func_no = 0; func_no < epc->max_functions; func_no++) { + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (ep_func) + continue; + + ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); + if (!ep_func) + goto err_remove_edma; + + ep_func->func_no = func_no; + ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, + PCI_CAP_ID_MSI); + ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, + PCI_CAP_ID_MSIX); + + list_add_tail(&ep_func->list, &ep->func_list); + } + + if (ep->ops->init) + ep->ops->init(ep); + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); @@ -651,14 +708,17 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) dw_pcie_dbi_ro_wr_dis(pci); return 0; + +err_remove_edma: + dw_pcie_edma_remove(pci); + + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); int dw_pcie_ep_init(struct dw_pcie_ep *ep) { int ret; - void *addr; - u8 func_no; struct resource *res; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -666,7 +726,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; const struct pci_epc_features *epc_features; - struct dw_pcie_ep_func *ep_func; INIT_LIST_HEAD(&ep->func_list); @@ -684,26 +743,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ep->ops->pre_init) ep->ops->pre_init(ep); - dw_pcie_version_detect(pci); - - dw_pcie_iatu_detect(pci); - - ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows, - GFP_KERNEL); - if (!ep->ib_window_map) - return -ENOMEM; - - ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows, - GFP_KERNEL); - if (!ep->ob_window_map) - return -ENOMEM; - - addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), - GFP_KERNEL); - if (!addr) - return -ENOMEM; - ep->outbound_addr = addr; - epc = devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { dev_err(dev, "Failed to create epc device\n"); @@ -717,23 +756,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ret < 0) epc->max_functions = 1; - for (func_no = 0; func_no < epc->max_functions; func_no++) { - ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); - if (!ep_func) - return -ENOMEM; - - ep_func->func_no = func_no; - ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, - PCI_CAP_ID_MSI); - ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, - PCI_CAP_ID_MSIX); - - list_add_tail(&ep_func->list, &ep->func_list); - } - - if (ep->ops->init) - ep->ops->init(ep); - ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, ep->page_size); if (ret < 0) { @@ -749,25 +771,25 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) goto err_exit_epc_mem; } - ret = dw_pcie_edma_detect(pci); - if (ret) - goto err_free_epc_mem; - if (ep->ops->get_features) { epc_features = ep->ops->get_features(ep); if (epc_features->core_init_notifier) return 0; } + /* + * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this + * step as platforms that implement 'core_init_notifier' feature may + * not have the hardware ready (i.e. core initialized) for access + * (Ex: tegra194). Any hardware access on such platforms result + * in system hang. + */ ret = dw_pcie_ep_init_complete(ep); if (ret) - goto err_remove_edma; + goto err_free_epc_mem; return 0; -err_remove_edma: - dw_pcie_edma_remove(pci); - err_free_epc_mem: pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, epc->mem->window.page_size);