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AJvYcCWbnnRJTKxJ5oNMS1NAnWj70rwywmTu6ZJU7wSyAfCj79s8X8buODtDSfENXHQOcKawmsqG+2G6dUN/awJTBKJYSEyaK32n600BYpaPnAQU0pKUL3HYQTkFa2A9ZIF5AttHPoBi2Ecv0r7byryD4nRi+SrYNp9p3kWl/8DP8iunY5i8mQ== X-Gm-Message-State: AOJu0Ywqud6q/wO8D46zk6cNygqu65fK1Bir8U0a/EebA+BAXxIaeD6Y msGyA1NOzs5tyQGZZiIzBw4bmHw0qOmXf7k54YM66NaPyj6nG2Bg X-Google-Smtp-Source: AGHT+IH5thlB/KqkhMFZEtOkS5tP1abakNep+y6JmIhXw52Gx1sgBN36fINQ3j2zydBdEGQM8NEAzQ== X-Received: by 2002:a05:600c:3b1d:b0:412:b0cc:1c62 with SMTP id m29-20020a05600c3b1d00b00412b0cc1c62mr1766054wms.32.1710498691351; Fri, 15 Mar 2024 03:31:31 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:ae92:6adf:5cb6:274c]) by smtp.gmail.com with ESMTPSA id l19-20020a05600c4f1300b004130378fb77sm8676549wmq.6.2024.03.15.03.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Mar 2024 03:31:30 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Chris Brandt , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/4] dt-bindings: i2c: renesas,riic: Document R9A09G057 support Date: Fri, 15 Mar 2024 10:30:30 +0000 Message-Id: <20240315103033.141226-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240315103033.141226-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240315103033.141226-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Document support for the I2C Bus Interface (RIIC) available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The RIIC interface in the Renesas RZ/V2H(P) differs from RZ/A in a couple of ways: - Register offsets for the RZ/V2H(P) SoC differ from those of the RZ/A SoC. - RZ/V2H register access is limited to 8-bit, whereas RZ/A supports 8/16/32-bit. - RZ/V2H has bit differences in the slave address register. To accommodate these differences in the existing driver, a new compatible string "renesas,riic-r9a09g057" is added. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring --- v1->v2 - Used a const for V2H SoC instead of enum in items list --- .../devicetree/bindings/i2c/renesas,riic.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml index 2291a7cd619b..91ecf17b7a81 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -15,14 +15,17 @@ allOf: properties: compatible: - items: - - enum: - - renesas,riic-r7s72100 # RZ/A1H - - renesas,riic-r7s9210 # RZ/A2M - - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five - - renesas,riic-r9a07g044 # RZ/G2{L,LC} - - renesas,riic-r9a07g054 # RZ/V2L - - const: renesas,riic-rz # RZ/A or RZ/G2L + oneOf: + - items: + - enum: + - renesas,riic-r7s72100 # RZ/A1H + - renesas,riic-r7s9210 # RZ/A2M + - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five + - renesas,riic-r9a07g044 # RZ/G2{L,LC} + - renesas,riic-r9a07g054 # RZ/V2L + - const: renesas,riic-rz # RZ/A or RZ/G2L + + - const: renesas,riic-r9a09g057 # RZ/V2H(P) reg: maxItems: 1