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AJvYcCVEuqF8LA1xUCUOfswO5BLr7jXFGJYKmaoC9euYXdpo6B1ZEb2NmcL/lx5n993vTA10+UMIgI8HSQYJI8pwgEf99o9cittjxRy73W7YbeWBSdwRmr3GcrzHorNqI72mmU7mOUPg4EapD9NBDVEl0uq6+9bF3hEGMR3zJNSVan7R6qOSKw== X-Gm-Message-State: AOJu0Yy1m47t00ZyBfnjZJFB7Xh+LFEulycVdAvRGL/F+KdkgMJNezCv RymyoaeBcOCaHhcG+GKGjjiC2L/ILUM0e1sf9tTMaF4Hl0sbjwNb X-Google-Smtp-Source: AGHT+IFDnBxiiHEGMW3NyZCKLBn1QZempbfU9J6p8Z/zwqhZ8ssIG6gBt+X+29f2ud2hwl0q2hvSzQ== X-Received: by 2002:adf:edc3:0:b0:33e:ca1f:1401 with SMTP id v3-20020adfedc3000000b0033eca1f1401mr2842809wro.4.1710854769424; Tue, 19 Mar 2024 06:26:09 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:3c11:2c6f:3ba9:bab]) by smtp.gmail.com with ESMTPSA id g4-20020adfe404000000b0033dd2a7167fsm12370020wrm.29.2024.03.19.06.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 06:26:08 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Chris Brandt , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar , Rob Herring Subject: [PATCH v3 1/4] dt-bindings: i2c: renesas,riic: Document R9A09G057 support Date: Tue, 19 Mar 2024 13:25:00 +0000 Message-Id: <20240319132503.80628-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240319132503.80628-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240319132503.80628-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Document support for the I2C Bus Interface (RIIC) available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The RIIC interface in the Renesas RZ/V2H(P) differs from RZ/A in a couple of ways: - Register offsets for the RZ/V2H(P) SoC differ from those of the RZ/A SoC. - RZ/V2H register access is limited to 8-bit, whereas RZ/A supports 8/16/32-bit. - RZ/V2H has bit differences in the slave address register. To accommodate these differences, a new compatible string "renesas,riic-r9a09g057" is added. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Reviewed-by: Wolfram Sang --- v2->v3 - Updated commit description v1->v2 - Used a const for V2H SoC instead of enum in items list --- .../devicetree/bindings/i2c/renesas,riic.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml index 2291a7cd619b..91ecf17b7a81 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -15,14 +15,17 @@ allOf: properties: compatible: - items: - - enum: - - renesas,riic-r7s72100 # RZ/A1H - - renesas,riic-r7s9210 # RZ/A2M - - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five - - renesas,riic-r9a07g044 # RZ/G2{L,LC} - - renesas,riic-r9a07g054 # RZ/V2L - - const: renesas,riic-rz # RZ/A or RZ/G2L + oneOf: + - items: + - enum: + - renesas,riic-r7s72100 # RZ/A1H + - renesas,riic-r7s9210 # RZ/A2M + - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five + - renesas,riic-r9a07g044 # RZ/G2{L,LC} + - renesas,riic-r9a07g054 # RZ/V2L + - const: renesas,riic-rz # RZ/A or RZ/G2L + + - const: renesas,riic-r9a09g057 # RZ/V2H(P) reg: maxItems: 1