| Message ID | 20240322144355.878930-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add SCIF support for Renesas RZ/V2H(P) SoC | expand |
On Fri, Mar 22, 2024 at 02:43:54PM +0000, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Document support for the Serial Communication Interface with FIFO (SCIF) > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L > (R9A07G044) SoC, with the following differences: > > - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready > and two for Rx and Tx buffer full, all of which are edge-triggered. > - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both > synchronous and asynchronous modes. > - There are differences in the configuration of certain registers such > as SCSMR, SCFCR, and SCSPTR between the two SoCs. > > To handle these differences in the driver, a new SoC-specific compatible > string is added, ensuring proper handling of the unique features and > register configurations of the RZ/V2H(P) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > --- > v3->v4 > - Appended the interrupts instead of adding SoC specific > - Added restriction for clocks and reset > > v2->v3 > - Added SoC specific compat string > --- > .../bindings/serial/renesas,scif.yaml | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml > index c13b31c28049..93fc7b75e2e5 100644 > --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml > +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml > @@ -79,6 +79,8 @@ properties: > - renesas,scif-r9a08g045 # RZ/G3S > - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback > > + - const: renesas,scif-r9a09g057 # RZ/V2H(P) > + > reg: > maxItems: 1 > > @@ -93,6 +95,9 @@ properties: > - description: Break interrupt > - description: Data Ready interrupt > - description: Transmit End interrupt > + - description: Transmit End/Data Ready interrupt > + - description: Receive buffer full interrupt (EDGE trigger) > + - description: Transmit buffer empty interrupt (EDGE trigger) > minItems: 4 > > interrupt-names: > @@ -104,6 +109,9 @@ properties: > - const: bri > - const: dri > - const: tei > + - const: tei-dri > + - const: rxi-edge > + - const: txi-edge > > clocks: > minItems: 1 > @@ -160,6 +168,7 @@ allOf: > - renesas,rcar-gen3-scif > - renesas,rcar-gen4-scif > - renesas,scif-r9a07g044 > + - renesas,scif-r9a09g057 > then: > required: > - resets > @@ -209,9 +218,30 @@ allOf: > properties: > interrupts: > minItems: 6 > + maxItems: 6 > > interrupt-names: > minItems: 6 > + maxItems: 6 > + > + - if: > + properties: > + compatible: > + contains: > + const: renesas,scif-r9a09g057 > + then: > + properties: > + clocks: > + maxItems: 1 > + > + clock-names: > + maxItems: 1 > + > + interrupts: > + minItems: 9 > + > + interrupt-names: > + minItems: 9 > > unevaluatedProperties: false > > -- > 2.34.1 >
On Fri, Mar 22, 2024 at 3:45 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Document support for the Serial Communication Interface with FIFO (SCIF) > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L > (R9A07G044) SoC, with the following differences: > > - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready > and two for Rx and Tx buffer full, all of which are edge-triggered. > - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both > synchronous and asynchronous modes. > - There are differences in the configuration of certain registers such > as SCSMR, SCFCR, and SCSPTR between the two SoCs. > > To handle these differences in the driver, a new SoC-specific compatible > string is added, ensuring proper handling of the unique features and > register configurations of the RZ/V2H(P) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v3->v4 > - Appended the interrupts instead of adding SoC specific > - Added restriction for clocks and reset Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index c13b31c28049..93fc7b75e2e5 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -79,6 +79,8 @@ properties: - renesas,scif-r9a08g045 # RZ/G3S - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback + - const: renesas,scif-r9a09g057 # RZ/V2H(P) + reg: maxItems: 1 @@ -93,6 +95,9 @@ properties: - description: Break interrupt - description: Data Ready interrupt - description: Transmit End interrupt + - description: Transmit End/Data Ready interrupt + - description: Receive buffer full interrupt (EDGE trigger) + - description: Transmit buffer empty interrupt (EDGE trigger) minItems: 4 interrupt-names: @@ -104,6 +109,9 @@ properties: - const: bri - const: dri - const: tei + - const: tei-dri + - const: rxi-edge + - const: txi-edge clocks: minItems: 1 @@ -160,6 +168,7 @@ allOf: - renesas,rcar-gen3-scif - renesas,rcar-gen4-scif - renesas,scif-r9a07g044 + - renesas,scif-r9a09g057 then: required: - resets @@ -209,9 +218,30 @@ allOf: properties: interrupts: minItems: 6 + maxItems: 6 interrupt-names: minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + const: renesas,scif-r9a09g057 + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + interrupts: + minItems: 9 + + interrupt-names: + minItems: 9 unevaluatedProperties: false