| Message ID | 20240625133008.2638902-1-niklas.soderlund+renesas@ragnatech.se (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: white-hawk: ethernet: Define AVB1 and AVB2 PHY | expand |
Hi Niklas, On Tue, Jun 25, 2024 at 3:31 PM Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> wrote: > Align with other Renesas SoCs and use the specific compatible for the > PHYs connected to AVB1 and AVB2, Marvell 88Q2110/QFN40. This allows > software to identify the PHY model at any time, regardless of the state > of the PHY reset line. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi > +++ b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi > @@ -27,7 +27,8 @@ mdio { > reset-post-delay-us = <4000>; > > avb1_phy: ethernet-phy@0 { > - compatible = "ethernet-phy-ieee802.3-c45"; > + compatible = "ethernet-phy-id002b.0980", > + "ethernet-phy-ieee802.3-c22"; > reg = <0>; > interrupt-parent = <&gpio6>; > interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > @@ -49,7 +50,8 @@ mdio { > reset-post-delay-us = <4000>; > > avb2_phy: ethernet-phy@0 { > - compatible = "ethernet-phy-ieee802.3-c45"; > + compatible = "ethernet-phy-id002b.0980", > + "ethernet-phy-ieee802.3-c22"; > reg = <0>; > interrupt-parent = <&gpio5>; > interrupts = <4 IRQ_TYPE_LEVEL_LOW>; Originally, I added explicit ethernet-phy-id* compatible values because Linux does not deassert the reset line before trying to read the PHY ID, hence failing. Have you checked if this is still the case after introducing the mdio subnode? I'd rather not add the explicit IDs, as board manufacturers may change the PHY revision or even the PHY model without notice. You can find my original test procedure, using kexec or bind/rebind, at https://lore.kernel.org/cover.1631174218.git.geert+renesas@glider.be/. Gr{oetje,eeting}s, Geert
Hi Geert, On 2024-06-25 16:54:38 +0200, Geert Uytterhoeven wrote: > Hi Niklas, > > On Tue, Jun 25, 2024 at 3:31 PM Niklas Söderlund > <niklas.soderlund+renesas@ragnatech.se> wrote: > > Align with other Renesas SoCs and use the specific compatible for the > > PHYs connected to AVB1 and AVB2, Marvell 88Q2110/QFN40. This allows > > software to identify the PHY model at any time, regardless of the state > > of the PHY reset line. > > > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi > > +++ b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi > > @@ -27,7 +27,8 @@ mdio { > > reset-post-delay-us = <4000>; > > > > avb1_phy: ethernet-phy@0 { > > - compatible = "ethernet-phy-ieee802.3-c45"; > > + compatible = "ethernet-phy-id002b.0980", > > + "ethernet-phy-ieee802.3-c22"; > > reg = <0>; > > interrupt-parent = <&gpio6>; > > interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > @@ -49,7 +50,8 @@ mdio { > > reset-post-delay-us = <4000>; > > > > avb2_phy: ethernet-phy@0 { > > - compatible = "ethernet-phy-ieee802.3-c45"; > > + compatible = "ethernet-phy-id002b.0980", > > + "ethernet-phy-ieee802.3-c22"; > > reg = <0>; > > interrupt-parent = <&gpio5>; > > interrupts = <4 IRQ_TYPE_LEVEL_LOW>; > > Originally, I added explicit ethernet-phy-id* compatible values because > Linux does not deassert the reset line before trying to read the PHY > ID, hence failing. Have you checked if this is still the case after > introducing the mdio subnode? I'd rather not add the explicit IDs, > as board manufacturers may change the PHY revision or even the PHY > model without notice. > > You can find my original test procedure, using kexec or bind/rebind, at > https://lore.kernel.org/cover.1631174218.git.geert+renesas@glider.be/. Indeed the mdio subnode reset do the trick without needing to hardcode the PHY compatible. At lest for RAVB, for the RTSN we still need to hardcode it as RTSN cant talk C45 when probing the PHY. Anyhow this patch can be dropped. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi index 595ec4ff4cdd..40a08b57b479 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi @@ -27,7 +27,8 @@ mdio { reset-post-delay-us = <4000>; avb1_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; + compatible = "ethernet-phy-id002b.0980", + "ethernet-phy-ieee802.3-c22"; reg = <0>; interrupt-parent = <&gpio6>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; @@ -49,7 +50,8 @@ mdio { reset-post-delay-us = <4000>; avb2_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; + compatible = "ethernet-phy-id002b.0980", + "ethernet-phy-ieee802.3-c22"; reg = <0>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
Align with other Renesas SoCs and use the specific compatible for the PHYs connected to AVB1 and AVB2, Marvell 88Q2110/QFN40. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)