diff mbox series

[v3,9/9] arm64: dts: renesas: rzg2ul: Set Ethernet PVDD to 1.8V

Message ID 20240625200316.4282-10-paul.barker.ct@bp.renesas.com (mailing list archive)
State Mainlined
Commit d98121492b0393924d96824f788d482e545e3605
Delegated to: Geert Uytterhoeven
Headers show
Series Configure GbEth for RGMII on RZ/G2L family | expand

Commit Message

Paul Barker June 25, 2024, 8:03 p.m. UTC 
On the RZ/G2UL & RZ/Five SMARC SOMs, the RGMII interface between the SoC
and the Ethernet PHY operates at 1.8V.

The power supply for this interface may be correctly configured in
u-boot, but the kernel should not be relying on this. Now that the
RZ/G2L pinctrl driver supports configuring the Ethernet power supply
voltage, we can simply specify the desired voltage in the device tree.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
Changes v2->v3:
  * Picked up Linus W's Acked-by tag.
Changes v1->v2:
  * Picked up Geert's Reviewed-by tag.

 .../boot/dts/renesas/rzg2ul-smarc-som.dtsi     | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 417f49090b15..79443fb3f581 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -144,6 +144,7 @@  adc_pins: adc {
 	eth0_pins: eth0 {
 		txc {
 			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
+			power-source = <1800>;
 			output-enable;
 		};
 
@@ -161,14 +162,19 @@  mux {
 				 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
 				 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
 				 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
-				 <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
-				 <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
+				 <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
+			power-source = <1800>;
+		};
+
+		irq {
+			pinmux = <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
 		};
 	};
 
 	eth1_pins: eth1 {
 		txc {
 			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
+			power-source = <1800>;
 			output-enable;
 		};
 
@@ -186,8 +192,12 @@  mux {
 				 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
 				 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
 				 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
-				 <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
-				 <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
+				 <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
+			power-source = <1800>;
+		};
+
+		irq {
+			pinmux = <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
 		};
 	};