From patchwork Tue Jun 25 20:03:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Barker X-Patchwork-Id: 13711998 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4C7BD17DE17; Tue, 25 Jun 2024 20:03:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345838; cv=none; b=GaBCVYLYIqHE9Io2y8gqa5BsNOg7V66c3qMPussNACbQFG66Bny3WgnffLpOjVm3RzJsoqXwvdX+zwlEb1A++nt2eWkplvOgq3L2s5X+DUlY5bZF+G/AzOdv9SKibm1t3oOmOKsQ2B1IyTSpLVsp0H96ewndsD8RA5kfjmJ4C3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719345838; c=relaxed/simple; bh=IHTD3Ly7Xevyu3XTOQjbSNBcLFMiOjRt71XjlcWTHiA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SGK+P60hEpv4BbqN4tS47YOASqccu4TeDYSJODC+5N3FZsykTuszByLrGPc43T4GIpmXgu7WfvqQpcdLDA11l/jGcpOcLW0wdpI4YNQsNkdDOl1k8KcN/JA7JJgfCJGiZQxOV9kZgXT0305VUG4DG16m1IhIlRK0ANjr0B4iLvE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.08,264,1712588400"; d="scan'208";a="209263979" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 26 Jun 2024 05:03:55 +0900 Received: from renesas-deb12.mshome.net (unknown [10.226.92.125]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 054D840078B4; Wed, 26 Jun 2024 05:03:50 +0900 (JST) From: Paul Barker To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Lad Prabhakar Cc: Paul Barker , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/9] arm64: dts: renesas: rzg2lc: Enable Ethernet TXC output Date: Tue, 25 Jun 2024 21:03:12 +0100 Message-Id: <20240625200316.4282-6-paul.barker.ct@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> References: <20240625200316.4282-1-paul.barker.ct@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/G2LC SMARC SoM, as per RGMII specification. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij --- Changes v2->v3: * Picked up Linus W's Acked-by tag. Changes v1->v2: * Picked up Geert's Reviewed-by tag. .../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 38 +++++++++++-------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 5e4209d6fb42..664311fd2098 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -128,22 +128,28 @@ &ostm2 { &pinctrl { eth0_pins: eth0 { - pinmux = , /* ET0_LINKSTA */ - , /* ET0_MDC */ - , /* ET0_MDIO */ - , /* ET0_TXC */ - , /* ET0_TX_CTL */ - , /* ET0_TXD0 */ - , /* ET0_TXD1 */ - , /* ET0_TXD2 */ - , /* ET0_TXD3 */ - , /* ET0_RXC */ - , /* ET0_RX_CTL */ - , /* ET0_RXD0 */ - , /* ET0_RXD1 */ - , /* ET0_RXD2 */ - , /* ET0_RXD3 */ - ; /* IRQ0 */ + txc { + pinmux = ; /* ET0_TXC */ + output-enable; + }; + + mux { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + , /* ET0_RXD3 */ + ; /* IRQ0 */ + }; }; gpio-sd0-pwr-en-hog {