| Message ID | 20240627161315.98143-4-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add CPG support for RZ/V2H(P) SoC | expand |
Hi Prabhakar, On Thu, Jun 27, 2024 at 6:14 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add RZ/V2H(P) CPG driver. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v2->v3 > - Added CLK_PLLDTY > - Added core clocks sys_0_pclk and iotop_0_shclk > - Dropped r9a09g057_crit_mod_clks Thanks for the update! > --- /dev/null > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > +static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { > + /* External Clock Inputs */ > + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), > + DEF_INPUT("rtxin", CLK_RTXIN), > + DEF_INPUT("qextal", CLK_QEXTAL), > + > + /* PLL Clocks */ > + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), > + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), > + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), > + > + /* Internal Core Clocks */ > + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), > + Missing comment "/* Core Clocks */"? > + DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), > + DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), > +}; > + > +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = { __initconst > + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), > +}; > + > +static const struct rzv2h_reset r9a09g057_resets[] = { > + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ > +}; > > +const struct rzv2h_cpg_info r9a09g057_cpg_info = { With my suggested changes to [2/3], these two can be __initconst, too. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Fri, Jul 12, 2024 at 1:00 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Thu, Jun 27, 2024 at 6:14 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add RZ/V2H(P) CPG driver. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v2->v3 > > - Added CLK_PLLDTY > > - Added core clocks sys_0_pclk and iotop_0_shclk > > - Dropped r9a09g057_crit_mod_clks > > Thanks for the update! > > > --- /dev/null > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > > > +static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { > > + /* External Clock Inputs */ > > + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), > > + DEF_INPUT("rtxin", CLK_RTXIN), > > + DEF_INPUT("qextal", CLK_QEXTAL), > > + > > + /* PLL Clocks */ > > + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), > > + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), > > + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), > > + > > + /* Internal Core Clocks */ > > + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), > > + > > Missing comment "/* Core Clocks */"? > Agreed. > > + DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), > > + DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), > > +}; > > + > > +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = { > > __initconst > OK. > > + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), > > +}; > > + > > +static const struct rzv2h_reset r9a09g057_resets[] = { > > + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ > > +}; > > > > +const struct rzv2h_cpg_info r9a09g057_cpg_info = { > > With my suggested changes to [2/3], these two can be __initconst, too. > Agreed. Cheers, Prabhakar
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index f078ccb635bb..76791a1c50ac 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -40,6 +40,7 @@ config CLK_RENESAS select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 + select CLK_R9A09G057 if ARCH_R9A09G057 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -193,6 +194,10 @@ config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A09G057 + bool "RZ/V2H(P) clock support" if COMPILE_TEST + select CLK_RZV2H + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d81a62e78345..23d2e26051c8 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o +obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c new file mode 100644 index 000000000000..8b2be17901b2 --- /dev/null +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/V2H(P) CPG driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/kernel.h> + +#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> + +#include "rzv2h-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK, + + /* External Input Clocks */ + CLK_AUDIO_EXTAL, + CLK_RTXIN, + CLK_QEXTAL, + + /* PLL Clocks */ + CLK_PLLCM33, + CLK_PLLDTY, + CLK_PLLCA55, + + /* Internal Core Clocks */ + CLK_PLLCM33_DIV16, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), + DEF_INPUT("rtxin", CLK_RTXIN), + DEF_INPUT("qextal", CLK_QEXTAL), + + /* PLL Clocks */ + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), + + /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + + DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), + DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), +}; + +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = { + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), +}; + +static const struct rzv2h_reset r9a09g057_resets[] = { + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ +}; + +const struct rzv2h_cpg_info r9a09g057_cpg_info = { + /* Core Clocks */ + .core_clks = r9a09g057_core_clks, + .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r9a09g057_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks), + .num_hw_mod_clks = 25 * 16, + + /* Resets */ + .resets = r9a09g057_resets, + .num_resets = ARRAY_SIZE(r9a09g057_resets), +}; diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 058d79673ae6..6d5427d82412 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -643,6 +643,10 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) } static const struct of_device_id rzv2h_cpg_match[] = { + { + .compatible = "renesas,r9a09g057-cpg", + .data = &r9a09g057_cpg_info, + }, { /* sentinel */ } }; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 2358782388c4..17a3c02528d6 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -156,4 +156,6 @@ struct rzv2h_cpg_info { unsigned int num_resets; }; +extern const struct rzv2h_cpg_info r9a09g057_cpg_info; + #endif /* __RENESAS_RZV2H_CPG_H__ */