| Message ID | 20240704061720.1444755-1-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: r8a779h0: Add PCIe clocks | expand |
On Thu, Jul 4, 2024 at 8:17 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add the PCIe module clock, which is used by the PCIe modules on the > Renesas R-Car V4M (R8A779H0) SoC. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.12. Gr{oetje,eeting}s, Geert
Hi Shimoda-san, On Thu, Jul 4, 2024 at 8:17 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add the PCIe module clock, which is used by the PCIe modules on the > Renesas R-Car V4M (R8A779H0) SoC. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > @@ -191,6 +191,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { > DEF_MOD("msi3", 621, R8A779H0_CLK_MSO), > DEF_MOD("msi4", 622, R8A779H0_CLK_MSO), > DEF_MOD("msi5", 623, R8A779H0_CLK_MSO), > + DEF_MOD("pciec0", 624, R8A779H0_CLK_S0D2_HSC), /me enables his magnifying glass Actually the bit is called "pcie0" in the MSTPCR6 documentation (Rev. 0.51), so I'll fix this up while applying. > DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), > DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4), > DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4), Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 079b55b30b23..74ef51387635 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -191,6 +191,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("msi3", 621, R8A779H0_CLK_MSO), DEF_MOD("msi4", 622, R8A779H0_CLK_MSO), DEF_MOD("msi5", 623, R8A779H0_CLK_MSO), + DEF_MOD("pciec0", 624, R8A779H0_CLK_S0D2_HSC), DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4), DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
Add the PCIe module clock, which is used by the PCIe modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+)