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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77488sm121546145e9.9.2024.07.16.03.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 03:30:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 06/11] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Tue, 16 Jul 2024 13:30:20 +0300 Message-Id: <20240716103025.1198495-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> References: <20240716103025.1198495-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Signed-off-by: Claudiu Beznea --- Changes in v2: - update compatibles - updated clocks and clock-names for clock-controller node - removed the power domain from the clock-controller as this is controlled by parent node in v2 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 0d5c47a65e46..78b4e088a3a5 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,30 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: vbattb@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + ranges = <0 0 0 0x1005c000 0 0x1000>; + interrupts = ; + interrupt-names = "tampdi"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>; + clock-names = "bclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + vbattclk: clock-controller@1c { + compatible = "renesas,r9a08g045-vbattb-clk"; + reg = <0 0x1c 0 0x10>; + clocks = <&vbattb_xtal>; + clock-names = "xin"; + #clock-cells = <0>; + status = "disabled"; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -299,4 +323,11 @@ timer { interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; };