diff mbox series

[RFT,5/6] arm64: dts: r8a779h0-gray-hawk-single: Add PWM support

Message ID 20240725194906.14644-13-wsa+renesas@sang-engineering.com (mailing list archive)
State Under Review
Delegated to: Geert Uytterhoeven
Headers show
Series PWM & TPU patches for V4M | expand

Commit Message

Wolfram Sang July 25, 2024, 7:49 p.m. UTC
This patch enables PWM channels 1+2 on the GrayHawk board. Only for
testing, not for upstream.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../dts/renesas/r8a779h0-gray-hawk-single.dts | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Geert Uytterhoeven July 29, 2024, 6:50 p.m. UTC | #1
Hi Wolfram,

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> This patch enables PWM channels 1+2 on the GrayHawk board. Only for
> testing, not for upstream.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

I looked at PWM1 and PWM2 with an oscilloscope on test points CP174
and CP175, and played with them using sysfs. Period and duty cycle
look fine, so
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

I had hoped to test PWM0, PWM3, and PWM4, too, as they are all available
on test points, but I couldn't locate CP238, CP240, and CP241.  The silk
screen for CP239 points underneath the heatsink, so probably all four
of them are obscured by the heatsink and/or switch board...

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
index 2b9a19bb1c5d..62878120673d 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
@@ -199,6 +199,16 @@  mmc_pins: mmc {
 		power-source = <1800>;
 	};
 
+	pwm1_pins: pwm1 {
+		groups = "pwm1_a";
+		function = "pwm1";
+	};
+
+	pwm2_pins: pwm2 {
+		groups = "pwm2_a";
+		function = "pwm2";
+	};
+
 	qspi0_pins: qspi0 {
 		groups = "qspi0_ctrl", "qspi0_data4";
 		function = "qspi0";
@@ -215,6 +225,20 @@  scif_clk2_pins: scif-clk2 {
 	};
 };
 
+&pwm1 {
+	pinctrl-0 = <&pwm1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &rpc {
 	pinctrl-0 = <&qspi0_pins>;
 	pinctrl-names = "default";