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AJvYcCXMUKJ59Y1r6xXWbd/3N0f9nv0xCZ1huNlZDHzj4oWO9ZZiiB9Gp1j23XhHrDmkUF7MQbpSmmK7ikoYwd35wPWWa+E3fbelbkgbNYpl9p10FAar5dGgJJ+4Pd8pt1H620sR33tsI9RD1g== X-Gm-Message-State: AOJu0YzGAqOjXquK7Edd0UzSivl+oZX/1L65IVT2043y8MCOcB61Hg9Z tBwSFpvPzPWj7cLF9Nt26qGJIXNSwml1IUHjEuTmhcLY4/xDc06Lu1rYOam3 X-Google-Smtp-Source: AGHT+IGb7yN1dD3SDk/C/zIlmrCO7f1xCMf4oF5BRleAsn9WR5r0oCGHM6Htd6kUGBWHTAfKRk4xRw== X-Received: by 2002:a05:600c:3b17:b0:428:9a1:f226 with SMTP id 5b1f17b1804b1-428243e1b22mr13203595e9.1.1722342381138; Tue, 30 Jul 2024 05:26:21 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:a2b2:16cc:b7df:405d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42813a5b3f6sm125366615e9.2.2024.07.30.05.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jul 2024 05:26:20 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Marc Zyngier , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/4] arm64: dts: renesas: r9a07g043u: Correct GICD and GICR sizes Date: Tue, 30 Jul 2024 13:24:34 +0100 Message-Id: <20240730122436.350013-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730122436.350013-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240730122436.350013-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The RZ/G2UL SoC is equipped with the GIC-600. The GICD is 64kB + 64kB for the MBI alias (in total 128kB), and the GICR is 128kB per CPU. Despite the RZ/G2UL SoC being single-core, it has two instances of GICR. Fixes: cf40c9689e510 ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Signed-off-by: Lad Prabhakar --- v1->v2 - Updated commit message --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 18ef297db933..20fb5e41c598 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -210,8 +210,8 @@ gic: interrupt-controller@11900000 { #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; + reg = <0x0 0x11900000 0 0x20000>, + <0x0 0x11940000 0 0x40000>; interrupts = ; }; };