| Message ID | 20240830203014.199326-3-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Enable serial NOR flash on RZ/G2UL SMARC EVK | expand |
Hi Geert, > -----Original Message----- > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: Friday, August 30, 2024 9:30 PM > Subject: [PATCH v2 RESEND 2/3] arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash > > Enable Renesas at25ql128a flash connected to QSPI0. > > Tested the flash by flashing bootloaders: > flash_erase /dev/mtd0 0 0 > flash_erase /dev/mtd1 0 0 > mtd_debug write /dev/mtd0 0 ${BL2_FILE_SIZE} ${BL2_IMAGE} mtd_debug write /dev/mtd1 512 > ${FIP_FILE_SIZE} ${FIP_IMAGE} > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v2->v2 resend: > * Rebased to next > v2: > * New patch. > --- > .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul- > smarc-som.dtsi > index 79443fb3f581..2e458cdc8888 100644 > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > @@ -201,6 +201,18 @@ irq { > }; > }; > > + qspi0_pins: qspi0 { > + qspi0-data { > + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; > + power-source = <1800>; > + }; > + > + qspi0-ctrl { > + pins = "QSPI0_SPCLK", "QSPI0_SSL"; > + power-source = <1800>; > + }; > + }; > + The pinctrl defintion like [1] and flash partition definitions like [2]. I will send V4 combining [1] and [2] [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20230901075932.105822-2-biju.das.jz@bp.renesas.com/ [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240830203014.199326-3-biju.das.jz@bp.renesas.com/ Cheers, Biju > sdhi0_emmc_pins: sd0emmc { > sd0_emmc_data { > pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", @@ -252,6 +264,42 @@ > sd0_mux_uhs { > }; > }; > > +&sbc { > + pinctrl-0 = <&qspi0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + m25p,fast-read; > + spi-max-frequency = <50000000>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <4>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + partition@0 { > + label = "bl2"; > + reg = <0x00000000 0x0001c000>; > + }; > + > + partition@1d000 { /* fip is at offset 0x200 */ > + label = "fip"; > + reg = <0x0001d000 0x7e3000>; > + }; > + > + partition@800000 { > + label = "user"; > + reg = <0x800000 0x800000>; > + }; > + }; > + }; > +}; > + > #if (SW_SW0_DEV_SEL) > &sdhi0 { > pinctrl-0 = <&sdhi0_emmc_pins>; > -- > 2.43.0
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 79443fb3f581..2e458cdc8888 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -201,6 +201,18 @@ irq { }; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL"; + power-source = <1800>; + }; + }; + sdhi0_emmc_pins: sd0emmc { sd0_emmc_data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", @@ -252,6 +264,42 @@ sd0_mux_uhs { }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x00000000 0x0001c000>; + }; + + partition@1d000 { /* fip is at offset 0x200 */ + label = "fip"; + reg = <0x0001d000 0x7e3000>; + }; + + partition@800000 { + label = "user"; + reg = <0x800000 0x800000>; + }; + }; + }; +}; + #if (SW_SW0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>;
Enable Renesas at25ql128a flash connected to QSPI0. Tested the flash by flashing bootloaders: flash_erase /dev/mtd0 0 0 flash_erase /dev/mtd1 0 0 mtd_debug write /dev/mtd0 0 ${BL2_FILE_SIZE} ${BL2_IMAGE} mtd_debug write /dev/mtd1 512 ${FIP_FILE_SIZE} ${FIP_IMAGE} Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v2->v2 resend: * Rebased to next v2: * New patch. --- .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+)