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AJvYcCUhRYcPLfPQnRyu4C2AhDoDs/CWibKG2riNpm0LrUXiMvW+d4atEaL5AEOsBsXaUz1JATBfjAhBEGgu@vger.kernel.org, AJvYcCV37QvoGybm0XwUaYcOtWsqUZLPcYbwpAeGwdGqCLAp5sEHvdnhDEixUaiJ01hFUG8M3G8jK5H9Ryevyq4G9Od9u9U=@vger.kernel.org, AJvYcCWe2dhStzsH9KAtQD2T4fP/Z1fvG7kXiPKvScTvhpf3fV1NEzRuUdlnADyBPHLIgEE8+dwMD9bACEmBv2Id@vger.kernel.org X-Gm-Message-State: AOJu0Yzj9RXdIwL5SAMrk7IviWvckjnhvZZQs9esGlNg1FBAMeVF7Kma jSO5RX14k4cUlYVMvhLr+j7vzKO8dWMctw72ualElMR2riGt+zRIjDXhCA== X-Google-Smtp-Source: AGHT+IHLKLaCyBdWJkVQ/RWROmiZmQC/XbMI9u2WV+co1SXbpQize0ns7wnFfIKxX37ujJwAkGHsww== X-Received: by 2002:a17:907:7203:b0:a90:c411:24fd with SMTP id a640c23a62f3a-a991bd052ddmr266321266b.10.1728045435142; Fri, 04 Oct 2024 05:37:15 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:2595:4364:d152:dff3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9910285ad0sm221601166b.34.2024.10.04.05.37.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 05:37:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/3] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger Date: Fri, 4 Oct 2024 13:36:58 +0100 Message-ID: <20241004123658.764557-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241004123658.764557-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241004123658.764557-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add support for configuring the multiplexed pins as schmitt-trigger inputs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea --- v1->v2 - Included RB tag --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 8d576cc74003..13708c71f938 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -140,6 +140,7 @@ #define PUPD(off) (0x1C00 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) #define NOD(off) (0x3000 + (off) * 8) +#define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) @@ -162,6 +163,7 @@ #define SR_MASK 0x01 #define PUPD_MASK 0x03 #define NOD_MASK 0x01 +#define SMT_MASK 0x01 #define PM_INPUT 0x1 #define PM_OUTPUT 0x2 @@ -1351,6 +1353,15 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); + if (!arg) + return -EINVAL; + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; @@ -1489,6 +1500,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL;