diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index a792a3e915fe..9e46b0ee6e80 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -348,6 +348,7 @@ config ARCH_R9A09G011
 
 config ARCH_R9A09G047
 	bool "ARM64 Platform support for RZ/G3E"
+	select SYSC_R9A09G047
 	help
 	  This enables support for the Renesas RZ/G3E SoC variants.
 
@@ -386,9 +387,14 @@ config RST_RCAR
 
 config SYSC_RZ
 	bool "System controller for RZ SoCs" if COMPILE_TEST
+	depends on MFD_SYSCON
 
 config SYSC_R9A08G045
 	bool "Renesas RZ/G3S System controller support" if COMPILE_TEST
 	select SYSC_RZ
 
+config SYSC_R9A09G047
+	bool "Renesas RZ/G3E System controller support" if COMPILE_TEST
+	select SYSC_RZ
+
 endif # SOC_RENESAS
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 8cd139b3dd0a..3256706112d9 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -7,6 +7,7 @@ ifdef CONFIG_SMP
 obj-$(CONFIG_ARCH_R9A06G032)	+= r9a06g032-smp.o
 endif
 obj-$(CONFIG_SYSC_R9A08G045)	+= r9a08g045-sysc.o
+obj-$(CONFIG_SYSC_R9A09G047)	+= r9a09g047-sysc.o
 
 # Family
 obj-$(CONFIG_PWC_RZV2M)		+= pwc-rzv2m.o
diff --git a/drivers/soc/renesas/r9a09g047-sysc.c b/drivers/soc/renesas/r9a09g047-sysc.c
new file mode 100644
index 000000000000..32bdab9f1774
--- /dev/null
+++ b/drivers/soc/renesas/r9a09g047-sysc.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G3E System controller driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include "rz-sysc.h"
+
+/* Register definitions */
+#define SYS_LSI_DEVID	0x304
+#define SYS_LSI_MODE	0x300
+#define SYS_LSI_PRR	0x308
+#define SYS_LSI_DEVID_REV	GENMASK(31, 28)
+#define SYS_LSI_DEVID_SPECIFIC	GENMASK(27, 0)
+#define SYS_LSI_PRR_CA55_DIS	BIT(8)
+#define SYS_LSI_PRR_NPU_DIS	BIT(1)
+/*
+ * BOOTPLLCA[1:0]
+ *	[0,0] => 1.1GHZ
+ *	[0,1] => 1.5GHZ
+ *	[1,0] => 1.6GHZ
+ *	[1,1] => 1.7GHZ
+ */
+#define SYS_LSI_MODE_STAT_BOOTPLLCA55	GENMASK(12, 11)
+#define SYS_LSI_MODE_CA55_1_7GHz	0x3
+
+static void rzg3e_extended_device_identification(struct device *dev,
+				void __iomem *sysc_base,
+				struct soc_device_attribute *soc_dev_attr)
+{
+	u32 prr_val, mode_val;
+	bool is_quad_core, npu_enabled;
+
+	prr_val = readl(sysc_base + SYS_LSI_PRR);
+	mode_val = readl(sysc_base + SYS_LSI_MODE);
+
+	/* Check CPU and NPU configuration */
+	is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
+	npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
+
+	dev_info(dev, "Detected Renesas %s Core %s %s Rev %s  %s\n",
+		 is_quad_core ? "Quad" : "Dual",
+		 soc_dev_attr->family,
+		 soc_dev_attr->soc_id,
+		 soc_dev_attr->revision,
+		 npu_enabled ? "with Ethos-U55" : "");
+
+	/* Check CA55 PLL configuration */
+	if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHz)
+		dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
+}
+
+static const struct rz_sysc_soc_id_init_data rzg3e_sysc_soc_id_init_data __initconst = {
+	.family = "RZ/G3E",
+	.id = 0x8679447,
+	.offset = SYS_LSI_DEVID,
+	.revision_mask = SYS_LSI_DEVID_REV,
+	.specific_id_mask = SYS_LSI_DEVID_SPECIFIC,
+	.extended_device_identification = rzg3e_extended_device_identification,
+};
+
+const struct rz_sysc_init_data rzg3e_sysc_init_data = {
+	.soc_id_init_data = &rzg3e_sysc_soc_id_init_data,
+};
diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c
index d34d295831b8..515eca249b6e 100644
--- a/drivers/soc/renesas/rz-sysc.c
+++ b/drivers/soc/renesas/rz-sysc.c
@@ -231,7 +231,7 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat
 
 	soc_id_start = strchr(match->compatible, ',') + 1;
 	soc_id_end = strchr(match->compatible, '-');
-	size = soc_id_end - soc_id_start;
+	size = soc_id_end - soc_id_start + 1;
 	if (size > 32)
 		size = 32;
 	strscpy(soc_id, soc_id_start, size);
@@ -257,8 +257,16 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat
 		return -ENODEV;
 	}
 
-	dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family,
-		 soc_dev_attr->soc_id, soc_dev_attr->revision);
+	/* Try to call SoC-specific device identification */
+	if (soc_data->extended_device_identification) {
+		soc_data->extended_device_identification(sysc->dev, sysc->base,
+							 soc_dev_attr);
+	} else {
+		dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n",
+			 soc_dev_attr->family,
+			 soc_dev_attr->soc_id,
+			 soc_dev_attr->revision);
+	}
 
 	soc_dev = soc_device_register(soc_dev_attr);
 	if (IS_ERR(soc_dev))
@@ -283,6 +291,9 @@ static struct regmap_config rz_sysc_regmap = {
 static const struct of_device_id rz_sysc_match[] = {
 #ifdef CONFIG_SYSC_R9A08G045
 	{ .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data },
+#endif
+#ifdef CONFIG_SYSC_R9A09G047
+	{ .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sysc_init_data },
 #endif
 	{ }
 };
@@ -315,20 +326,25 @@ static int rz_sysc_probe(struct platform_device *pdev)
 		return ret;
 
 	data = match->data;
-	if (!data->max_register_offset)
-		return -EINVAL;
+	if (data->signals_init_data) {
+		if (!data->max_register_offset)
+			return -EINVAL;
 
-	ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals);
-	if (ret)
-		return ret;
+		ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals);
+		if (ret)
+			return ret;
+
+		rz_sysc_regmap.max_register = data->max_register_offset;
+		dev_set_drvdata(dev, sysc);
 
-	dev_set_drvdata(dev, sysc);
-	rz_sysc_regmap.max_register = data->max_register_offset;
-	regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap);
-	if (IS_ERR(regmap))
-		return PTR_ERR(regmap);
+		regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap);
+		if (IS_ERR(regmap))
+			return PTR_ERR(regmap);
 
-	return of_syscon_register_regmap(dev->of_node, regmap);
+		return of_syscon_register_regmap(dev->of_node, regmap);
+	}
+
+	return 0;
 }
 
 static struct platform_driver rz_sysc_driver = {
diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h
index babca9c743c7..2b5ad41cef9e 100644
--- a/drivers/soc/renesas/rz-sysc.h
+++ b/drivers/soc/renesas/rz-sysc.h
@@ -8,7 +8,9 @@
 #ifndef __SOC_RENESAS_RZ_SYSC_H__
 #define __SOC_RENESAS_RZ_SYSC_H__
 
+#include <linux/device.h>
 #include <linux/refcount.h>
+#include <linux/sys_soc.h>
 #include <linux/types.h>
 
 /**
@@ -42,6 +44,7 @@ struct rz_sysc_signal {
  * @offset: SYSC SoC ID register offset
  * @revision_mask: SYSC SoC ID revision mask
  * @specific_id_mask: SYSC SoC ID specific ID mask
+ * @extended_device_identification: SoC-specific extended device identification
  */
 struct rz_sysc_soc_id_init_data {
 	const char * const family;
@@ -49,6 +52,9 @@ struct rz_sysc_soc_id_init_data {
 	u32 offset;
 	u32 revision_mask;
 	u32 specific_id_mask;
+	void (*extended_device_identification)(struct device *dev,
+		void __iomem *sysc_base,
+		struct soc_device_attribute *soc_dev_attr);
 };
 
 /**
@@ -65,6 +71,7 @@ struct rz_sysc_init_data {
 	u32 max_register_offset;
 };
 
+extern const struct rz_sysc_init_data rzg3e_sysc_init_data;
 extern const struct rz_sysc_init_data rzg3s_sysc_init_data;
 
 #endif /* __SOC_RENESAS_RZ_SYSC_H__ */
