From patchwork Fri Dec 13 17:38:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907570 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1D48C1E5018; Fri, 13 Dec 2024 17:39:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111572; cv=none; b=a/cJEnVCRc4jXNbXqD2BNRDMZqjRvrcEXa7FxN99iaPhNTIgUhazRsTY61bSq1YDdZ6hiVINLfY2dErLg+o7SzcBGHj/7xqTK/K0DULbRuonZO/klqepcQKm9iUlbDFlF4HLskYWKR1xjuo4NiPj3zaTy7d46i7btgOt6HBrmYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111572; c=relaxed/simple; bh=v3EGrAGGDM80tSIv2wUo5naY6BCzldYafsuJC2o4BFc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qV/02/2lhkao5DFuf9OnAZdz2a+aEViyDpfUvMGplIvHIls8cMOj+DhHJjYfhO/GR844K4cWkGnkZmCtPd8mEL1pUi6ceCTUKiy24vmSfMOL0ZokBQSpW9w891vohyYSI1aPbCD2f3FJzy/8h+tGe+ydwGdBDEzk+h3+f6+KK7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: sEK98c/yT1yymOAc+1Ctmw== X-CSE-MsgGUID: wZ528GqrRVGA5Oyj5XazhQ== X-IronPort-AV: E=Sophos;i="6.12,231,1728918000"; d="scan'208";a="227797735" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3C0454006DF1; Sat, 14 Dec 2024 02:39:15 +0900 (JST) From: Biju Das To: Linus Walleij Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 3/7] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table Date: Fri, 13 Dec 2024 17:38:49 +0000 Message-ID: <20241213173901.599226-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently r9a09g057_variable_pin_cfg table uses port 11 instead of port PB as mentioned in the hardware manual. Update the r9a09g057_variable_pin_cfg table with alpha-numeric port names to match with the hardware manual. Signed-off-by: Biju Das --- v3: * New patch. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 1a7be7d7b520..67d776feb42d 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -382,12 +382,12 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, } static const u64 r9a09g057_variable_pin_cfg[] = { - RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), }; #ifdef CONFIG_RISCV