diff mbox series

[10/11] irqchip/renesas-rzv2h: Add RZ/G3E support

Message ID 20250120094715.25802-11-biju.das.jz@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Add Support for RZ/G3E ICU | expand

Commit Message

Biju Das Jan. 20, 2025, 9:47 a.m. UTC 
The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register offset starts at 0x830 instead of 0x30.
 - The number of GPIO interrupts for TINT selection is 141 instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 15 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
adding LUT for mapping between pin index and TINT selection index.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 47 +++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

Comments

Fabrizio Castro Jan. 23, 2025, 9:45 a.m. UTC | #1 
Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 10/11] irqchip/renesas-rzv2h: Add RZ/G3E support
> 
> The ICU block on the RZ/G3E SoC is almost identical to the one found on
> the RZ/V2H SoC, with the following differences:
>  - The TINT register offset starts at 0x830 instead of 0x30.
>  - The number of GPIO interrupts for TINT selection is 141 instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 15 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
> adding LUT for mapping between pin index and TINT selection index.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 47 +++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index a1ca34d33c93..a0d79b357379 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -75,6 +75,7 @@
> 
>  /**
>   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
> + * @tssel_lut: TINT lookup table
>   * @t_offs: TINT offset
>   * @tien: TIEN mask
>   * @tssel_mask: TSSEL mask
> @@ -83,6 +84,7 @@
>   * @tssr_k: TSSR index k
>   */
>  struct rzv2h_hw_info {
> +	const u8 *tssel_lut;
>  	u16 t_offs;
>  	u16 tien;
>  	u16 tssel_mask;
> @@ -306,6 +308,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  	if (tint > priv->info->max_tssel)
>  		return -EINVAL;
> 
> +	if (priv->info->tssel_lut)
> +		tint = priv->info->tssel_lut[tint & 0xff];
> +
>  	hwirq = irqd_to_hwirq(d);
>  	tint_nr = hwirq - ICU_TINT_START;
> 
> @@ -514,6 +519,42 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
>  	return ret;
>  }
> 
> +/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
> +static const u8 rzg3e_tssel_lut[] = {
> +	81, 82, 83, 84, 85, 86, 87, 88,		/* P00-P07 */
> +	89, 90, 91, 92, 93, 94, 95, 96,		/* P10-P17 */
> +	111, 112,				/* P20-P21 */
> +	97, 98, 99, 100, 101, 102, 103, 104,	/* P30-P37 */
> +	105, 106, 107, 108, 109, 110,		/* P40-P45 */
> +	113, 114, 115, 116, 117, 118, 119,	/* P50-P56 */
> +	120, 121, 122, 123, 124, 125, 126,	/* P60-P66 */
> +	127, 128, 129, 130, 131, 132, 133, 134,	/* P70-P77 */
> +	135, 136, 137, 138, 139, 140,		/* P80-P85 */
> +	43, 44, 45, 46, 47, 48, 49, 50,		/* PA0-PA7 */
> +	51, 52, 53, 54, 55, 56, 57, 58,		/* PB0-PB7 */
> +	59, 60,	61,				/* PC0-PC2 */
> +	62, 63, 64, 65, 66, 67, 68, 69,		/* PD0-PD7 */
> +	70, 71, 72, 73, 74, 75, 76, 77,		/* PE0-PE7 */
> +	78, 79, 80,				/* PF0-PF2 */
> +	25, 26, 27, 28, 29, 30, 31, 32,		/* PG0-PG7 */
> +	33, 34, 35, 36, 37, 38,			/* PH0-PH5 */
> +	4, 5, 6, 7, 8,				/* PJ0-PJ4 */
> +	39, 40, 41, 42,				/* PK0-PK3 */
> +	9, 10, 11, 12, 21, 22, 23, 24,		/* PL0-PL7 */
> +	13, 14, 15, 16, 17, 18, 19, 20,		/* PM0-PM7 */
> +	0, 1, 2, 3				/* PS0-PS3 */
> +};
> +
> +static const struct rzv2h_hw_info rzg3e_hw_params = {
> +	.tssel_lut = rzg3e_tssel_lut,
> +	.t_offs = 0x800,
> +	.max_tssel = 0x8c,
> +	.tien = BIT(15),
> +	.tssel_mask = GENMASK(7, 0),
> +	.tssel_shift = 16,
> +	.tssr_k = 2,
> +};
> +
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs = 0,
>  	.max_tssel = 0x55,
> @@ -523,12 +564,18 @@ static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.tssr_k = 4,
>  };
> 
> +static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
> +{
> +	return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
> +}
> +
>  static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
>  {
>  	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
>  }
> 
>  IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
> +IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
>  IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
>  IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
>  MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
> --
> 2.43.0
>
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index a1ca34d33c93..a0d79b357379 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -75,6 +75,7 @@ 
 
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tssel_lut: TINT lookup table
  * @t_offs: TINT offset
  * @tien: TIEN mask
  * @tssel_mask: TSSEL mask
@@ -83,6 +84,7 @@ 
  * @tssr_k: TSSR index k
  */
 struct rzv2h_hw_info {
+	const u8 *tssel_lut;
 	u16 t_offs;
 	u16 tien;
 	u16 tssel_mask;
@@ -306,6 +308,9 @@  static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	if (tint > priv->info->max_tssel)
 		return -EINVAL;
 
+	if (priv->info->tssel_lut)
+		tint = priv->info->tssel_lut[tint & 0xff];
+
 	hwirq = irqd_to_hwirq(d);
 	tint_nr = hwirq - ICU_TINT_START;
 
@@ -514,6 +519,42 @@  static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 	return ret;
 }
 
+/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
+static const u8 rzg3e_tssel_lut[] = {
+	81, 82, 83, 84, 85, 86, 87, 88,		/* P00-P07 */
+	89, 90, 91, 92, 93, 94, 95, 96,		/* P10-P17 */
+	111, 112,				/* P20-P21 */
+	97, 98, 99, 100, 101, 102, 103, 104,	/* P30-P37 */
+	105, 106, 107, 108, 109, 110,		/* P40-P45 */
+	113, 114, 115, 116, 117, 118, 119,	/* P50-P56 */
+	120, 121, 122, 123, 124, 125, 126,	/* P60-P66 */
+	127, 128, 129, 130, 131, 132, 133, 134,	/* P70-P77 */
+	135, 136, 137, 138, 139, 140,		/* P80-P85 */
+	43, 44, 45, 46, 47, 48, 49, 50,		/* PA0-PA7 */
+	51, 52, 53, 54, 55, 56, 57, 58,		/* PB0-PB7 */
+	59, 60,	61,				/* PC0-PC2 */
+	62, 63, 64, 65, 66, 67, 68, 69,		/* PD0-PD7 */
+	70, 71, 72, 73, 74, 75, 76, 77,		/* PE0-PE7 */
+	78, 79, 80,				/* PF0-PF2 */
+	25, 26, 27, 28, 29, 30, 31, 32,		/* PG0-PG7 */
+	33, 34, 35, 36, 37, 38,			/* PH0-PH5 */
+	4, 5, 6, 7, 8,				/* PJ0-PJ4 */
+	39, 40, 41, 42,				/* PK0-PK3 */
+	9, 10, 11, 12, 21, 22, 23, 24,		/* PL0-PL7 */
+	13, 14, 15, 16, 17, 18, 19, 20,		/* PM0-PM7 */
+	0, 1, 2, 3				/* PS0-PS3 */
+};
+
+static const struct rzv2h_hw_info rzg3e_hw_params = {
+	.tssel_lut = rzg3e_tssel_lut,
+	.t_offs = 0x800,
+	.max_tssel = 0x8c,
+	.tien = BIT(15),
+	.tssel_mask = GENMASK(7, 0),
+	.tssel_shift = 16,
+	.tssr_k = 2,
+};
+
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs = 0,
 	.max_tssel = 0x55,
@@ -523,12 +564,18 @@  static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.tssr_k = 4,
 };
 
+static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
+{
+	return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
+}
+
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 {
 	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
 }
 
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
+IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");