| Message ID | 20250120094715.25802-8-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Support for RZ/G3E ICU | expand |
Hi Biju, Thanks for your patch! > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: 20 January 2025 09:47 > Subject: [PATCH 07/11] irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info > > On RZ/G3E the number of TSSR registers is 15 compared to 8 on RZ/V2H and > each TSSR register can program 2 TINTs compared to 4 on RZ/V2H. > > Add tssr_k variable to struct rzv2h_hw_info to handle this difference and > drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Cheers, Fab > --- > drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c > index b244cd61cba4..a9a9723ff4bb 100644 > --- a/drivers/irqchip/irq-renesas-rzv2h.c > +++ b/drivers/irqchip/irq-renesas-rzv2h.c > @@ -64,8 +64,6 @@ > #define ICU_TINT_LEVEL_HIGH 2 > #define ICU_TINT_LEVEL_LOW 3 > > -#define ICU_TSSR_K(tint_nr) ((tint_nr) / 4) > -#define ICU_TSSR_TSSEL_N(tint_nr) ((tint_nr) % 4) > #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) > #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) > #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) > @@ -83,10 +81,12 @@ > * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. > * @t_offs: TINT offset > * @max_tssel: TSSEL max value > + * @tssr_k: TSSR index k > */ > struct rzv2h_hw_info { > u16 t_offs; > u8 max_tssel; > + u8 tssr_k; > }; > > /** > @@ -144,8 +144,8 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) > return; > > tint_nr = hw_irq - ICU_TINT_START; > - k = ICU_TSSR_K(tint_nr); > - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); > + k = tint_nr / priv->info->tssr_k; > + tssel_n = tint_nr % priv->info->tssr_k; > > guard(raw_spinlock)(&priv->lock); > tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); > @@ -307,8 +307,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > hwirq = irqd_to_hwirq(d); > tint_nr = hwirq - ICU_TINT_START; > > - tssr_k = ICU_TSSR_K(tint_nr); > - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); > + tssr_k = tint_nr / priv->info->tssr_k; > + tssel_n = tint_nr % priv->info->tssr_k; > > titsr_k = ICU_TITSR_K(tint_nr); > titsel_n = ICU_TITSR_TITSEL_N(tint_nr); > @@ -515,6 +515,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p > static const struct rzv2h_hw_info rzv2h_hw_params = { > .t_offs = 0, > .max_tssel = 0x55, > + .tssr_k = 4, > }; > > static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) > -- > 2.43.0 >
diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index b244cd61cba4..a9a9723ff4bb 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_K(tint_nr) ((tint_nr) / 4) -#define ICU_TSSR_TSSEL_N(tint_nr) ((tint_nr) % 4) #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) @@ -83,10 +81,12 @@ * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset * @max_tssel: TSSEL max value + * @tssr_k: TSSR index k */ struct rzv2h_hw_info { u16 t_offs; u8 max_tssel; + u8 tssr_k; }; /** @@ -144,8 +144,8 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) return; tint_nr = hw_irq - ICU_TINT_START; - k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + k = tint_nr / priv->info->tssr_k; + tssel_n = tint_nr % priv->info->tssr_k; guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); @@ -307,8 +307,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) hwirq = irqd_to_hwirq(d); tint_nr = hwirq - ICU_TINT_START; - tssr_k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + tssr_k = tint_nr / priv->info->tssr_k; + tssel_n = tint_nr % priv->info->tssr_k; titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); @@ -515,6 +515,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = 0x55, + .tssr_k = 4, }; static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
On RZ/G3E the number of TSSR registers is 15 compared to 8 on RZ/V2H and each TSSR register can program 2 TINTs compared to 4 on RZ/V2H. Add tssr_k variable to struct rzv2h_hw_info to handle this difference and drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)