| Message ID | 20250120094715.25802-9-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Support for RZ/G3E ICU | expand |
Hi Biju, Thanks for your patch! > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: 20 January 2025 09:47 > Subject: [PATCH 08/11] irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to struct > rzv2h_hw_info > > On RZ/G3E each TSSR register can program 2 TINTs compared to 4 TINTs on > RZ/V2H. Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info > to simplify the calculations when we add support for RZ/G3E and drop the > macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Cheers, Fab > --- > drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c > index a9a9723ff4bb..5990dcf72ef0 100644 > --- a/drivers/irqchip/irq-renesas-rzv2h.c > +++ b/drivers/irqchip/irq-renesas-rzv2h.c > @@ -64,8 +64,6 @@ > #define ICU_TINT_LEVEL_HIGH 2 > #define ICU_TINT_LEVEL_LOW 3 > > -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) > -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) > #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) > > #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) > @@ -80,11 +78,15 @@ > /** > * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. > * @t_offs: TINT offset > + * @tssel_mask: TSSEL mask > + * @tssel_shift: TSSEL shift > * @max_tssel: TSSEL max value > * @tssr_k: TSSR index k > */ > struct rzv2h_hw_info { > u16 t_offs; > + u16 tssel_mask; > + u8 tssel_shift; > u8 max_tssel; > u8 tssr_k; > }; > @@ -317,8 +319,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > guard(raw_spinlock)(&priv->lock); > > tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); > - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); > - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); > + tssr &= ~((priv->info->tssel_mask << (tssel_n * priv->info->tssel_shift)) | tien); > + tssr |= (tint << (tssel_n * priv->info->tssel_shift)); > > writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); > > @@ -515,6 +517,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p > static const struct rzv2h_hw_info rzv2h_hw_params = { > .t_offs = 0, > .max_tssel = 0x55, > + .tssel_mask = GENMASK(6, 0), > + .tssel_shift = 8, > .tssr_k = 4, > }; > > -- > 2.43.0 >
diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index a9a9723ff4bb..5990dcf72ef0 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) @@ -80,11 +78,15 @@ /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @tssel_mask: TSSEL mask + * @tssel_shift: TSSEL shift * @max_tssel: TSSEL max value * @tssr_k: TSSR index k */ struct rzv2h_hw_info { u16 t_offs; + u16 tssel_mask; + u8 tssel_shift; u8 max_tssel; u8 tssr_k; }; @@ -317,8 +319,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); + tssr &= ~((priv->info->tssel_mask << (tssel_n * priv->info->tssel_shift)) | tien); + tssr |= (tint << (tssel_n * priv->info->tssel_shift)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); @@ -515,6 +517,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = 0x55, + .tssel_mask = GENMASK(6, 0), + .tssel_shift = 8, .tssr_k = 4, };
On RZ/G3E each TSSR register can program 2 TINTs compared to 4 TINTs on RZ/V2H. Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info to simplify the calculations when we add support for RZ/G3E and drop the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)