| Message ID | 20250126134616.37334-7-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add RZ/G3E SDHI support | expand |
On Sun, Jan 26, 2025 at 01:46:08PM +0000, Biju Das wrote: > Enable eMMC on SDHI0 and SD on SDHI2 on RZ/G3E SMARC SoM. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 89 +++++++++++++++++++ > 1 file changed, 89 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi > index f4ba050beb0d..81f4f738482b 100644 > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi > @@ -8,17 +8,79 @@ > / { > compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; > > + aliases { > + mmc0 = &sdhi0; > + mmc2 = &sdhi2; > + }; > + > memory@48000000 { > device_type = "memory"; > /* First 128MB is reserved for secure area. */ > reg = <0x0 0x48000000 0x0 0xf8000000>; > }; > + > + reg_3p3v: regulator-3p3v { > + compatible = "regulator-fixed"; > + regulator-name = "fixed-3.3V"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > }; > > &audio_extal_clk { > clock-frequency = <48000000>; > }; > > +&pinctrl { > + sdhi0_emmc_pins: sd0emmc { > + sd0-emmc-ctrl { > + pins = "SD0CLK", "SD0CMD"; > + renesas,output-impedance = <3>; > + }; > + > + sd0-iovs { > + pins = "SD0IOVS"; > + renesas,output-impedance = <3>; > + }; > + > + sd0-emmc-data { > + pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", > + "SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7"; > + renesas,output-impedance = <3>; > + }; > + > + sd0-emmc-rst { > + pins = "SD0RSTN"; > + renesas,output-impedance = <3>; > + }; > + }; > + > + sdhi2_pins: sd2 { > + sd2-cd { > + pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */ > + }; > + > + sd2-io { > + pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>, /* SD2IOVS */ > + <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2IOPWEN */ > + }; > + > + sd2-data { > + pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */ > + <RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */ > + <RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */ > + <RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */ > + }; > + > + sd2-ctrl { > + pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */ > + <RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */ > + }; > + }; > +}; > + > &qextal_clk { > clock-frequency = <24000000>; > }; > @@ -27,6 +89,33 @@ &rtxin_clk { > clock-frequency = <32768>; > }; > > +&sdhi0 { > + pinctrl-0 = <&sdhi0_emmc_pins>; > + pinctrl-1 = <&sdhi0_emmc_pins>; > + pinctrl-names = "default", "state_uhs"; > + > + vmmc-supply = <®_3p3v>; > + vqmmc-supply = <&vqmmc_sdhi0>; > + bus-width = <8>; > + mmc-hs200-1_8v; > + non-removable; > + fixed-emmc-driver-type = <1>; > + status = "okay"; > +}; > + > +&sdhi2 { > + pinctrl-0 = <&sdhi2_pins>; > + pinctrl-1 = <&sdhi2_pins>; > + pinctrl-names = "default", "state_uhs"; > + > + vmmc-supply = <®_3p3v>; > + vqmmc-supply = <&vqmmc_sdhi2>; > + bus-width = <4>; > + sd-uhs-sdr50; > + sd-uhs-sdr104; > + status = "okay"; > +}; > + > &wdt1 { > status = "okay"; > }; > -- > 2.43.0 > Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
On Sun, 26 Jan 2025 at 14:46, Biju Das <biju.das.jz@bp.renesas.com> wrote: > Enable eMMC on SDHI0 and SD on SDHI2 on RZ/G3E SMARC SoM. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index f4ba050beb0d..81f4f738482b 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -8,17 +8,79 @@ / { compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + aliases { + mmc0 = &sdhi0; + mmc2 = &sdhi2; + }; + memory@48000000 { device_type = "memory"; /* First 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0xf8000000>; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &audio_extal_clk { clock-frequency = <48000000>; }; +&pinctrl { + sdhi0_emmc_pins: sd0emmc { + sd0-emmc-ctrl { + pins = "SD0CLK", "SD0CMD"; + renesas,output-impedance = <3>; + }; + + sd0-iovs { + pins = "SD0IOVS"; + renesas,output-impedance = <3>; + }; + + sd0-emmc-data { + pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", + "SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7"; + renesas,output-impedance = <3>; + }; + + sd0-emmc-rst { + pins = "SD0RSTN"; + renesas,output-impedance = <3>; + }; + }; + + sdhi2_pins: sd2 { + sd2-cd { + pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */ + }; + + sd2-io { + pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>, /* SD2IOVS */ + <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2IOPWEN */ + }; + + sd2-data { + pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */ + <RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */ + <RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */ + <RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */ + }; + + sd2-ctrl { + pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */ + <RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */ + }; + }; +}; + &qextal_clk { clock-frequency = <24000000>; }; @@ -27,6 +89,33 @@ &rtxin_clk { clock-frequency = <32768>; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi0>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi2>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + &wdt1 { status = "okay"; };
Enable eMMC on SDHI0 and SD on SDHI2 on RZ/G3E SMARC SoM. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+)