From patchwork Tue Jan 28 10:47:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13952445 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 11D9E19340D; Tue, 28 Jan 2025 10:48:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738061301; cv=none; b=dvzhI4w0/+9pJu1JiHratD6hS2MWX/ymOo1GC/9coRj4ynLt956P+SUs6y9a5Deyn36zxgiGn58CAdoNH9ZX61OZdQ6Is+jX+DJIKbvK3Vv4ul6Seyaq1JQI4cWBn8p+5Gxbhx8CSJ8JSgcPUBc9L/AEKx0eaoyz+TX8CcLZCUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738061301; c=relaxed/simple; bh=DuYLcu4oh2l1ypcpXuc+en1YT4M5z6jn6b33ze7xF9c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TlFBMuVjO37S/0WpdRFT6bmSKF0QXa8Ieio2aVu+jvcuPrGeEEG9tjA15fARDGU+nN/Ud+q07xrP5DNGeZU92mz1I2nbc5QS3fDMOzfnvAsOEp2ui485mNjaJrP0ckeyoYhVc+/jrsGD1PD5Sgio9S1TUSTSKl9aBKsPlOkfnqk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: hG8JVvdMQDSFgxEBDD81Mg== X-CSE-MsgGUID: wFMN+ys6RFCrBjoI5RHIdA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 28 Jan 2025 19:48:18 +0900 Received: from localhost.localdomain (unknown [10.226.93.131]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9A63B41FB5AD; Tue, 28 Jan 2025 19:47:58 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Fabrizio Castro , Tommaso Merciai Subject: [PATCH v3 13/13] arm64: dts: renesas: r9a09g047: Add icu node Date: Tue, 28 Jan 2025 10:47:03 +0000 Message-ID: <20250128104714.80807-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250128104714.80807-1-biju.das.jz@bp.renesas.com> References: <20250128104714.80807-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI and add icu as interrupt-parent of pincontrol. Also, define the ICU IRQs for board DT users. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Collected tags. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index c93aa16d0a6e..2023f70d3329 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -8,6 +8,24 @@ #include #include +#define RZG3E_NMI 0 +#define RZG3E_IRQ0 1 +#define RZG3E_IRQ1 2 +#define RZG3E_IRQ2 3 +#define RZG3E_IRQ3 4 +#define RZG3E_IRQ4 5 +#define RZG3E_IRQ5 6 +#define RZG3E_IRQ6 7 +#define RZG3E_IRQ7 8 +#define RZG3E_IRQ8 9 +#define RZG3E_IRQ9 10 +#define RZG3E_IRQ10 11 +#define RZG3E_IRQ11 12 +#define RZG3E_IRQ12 13 +#define RZG3E_IRQ13 14 +#define RZG3E_IRQ14 15 +#define RZG3E_IRQ15 16 + / { compatible = "renesas,r9a09g047"; #address-cells = <2>; @@ -131,6 +149,95 @@ soc: soc { #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g047-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g047-pinctrl"; reg = <0 0x10410000 0 0x10000>; @@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 232>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; };