diff mbox series

[v3,01/13] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC

Message ID 20250128104714.80807-2-biju.das.jz@bp.renesas.com (mailing list archive)
State New
Delegated to: Geert Uytterhoeven
Headers show
Series Add Support for RZ/G3E ICU | expand

Commit Message

Biju Das Jan. 28, 2025, 10:46 a.m. UTC 
Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
SoC is almost identical to the one found on the RZ/V2H SoC, with the
following differences:
 - The TINT register offset is 0x830 compared to 0x30 on RZ/V2H.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 15 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Collected tags.
---
 .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml    | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Geert Uytterhoeven Jan. 28, 2025, 3:17 p.m. UTC | #1 
Hi Biju,

Thanks for your patch!

On Tue, 28 Jan 2025 at 11:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
> SoC is almost identical to the one found on the RZ/V2H SoC, with the
> following differences:
>  - The TINT register offset is 0x830 compared to 0x30 on RZ/V2H.

The first TINT register is at offset 0x820 vs. 0x20.
Perhaps:

   - The TINT register base offset is 0x800 instead of zero.

>  - The number of supported GPIO interrupts for TINT selection is 141
>    instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 15 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
>
> Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
> SoC.
>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Biju Das Jan. 30, 2025, 11:11 a.m. UTC | #2 
Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 28 January 2025 15:17
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH v3 01/13] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
> SoC
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Tue, 28 Jan 2025 at 11:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
> > SoC is almost identical to the one found on the RZ/V2H SoC, with the
> > following differences:
> >  - The TINT register offset is 0x830 compared to 0x30 on RZ/V2H.
> 
> The first TINT register is at offset 0x820 vs. 0x20.
> Perhaps:
> 
>    - The TINT register base offset is 0x800 instead of zero.

OK, will fix this.

> 
> >  - The number of supported GPIO interrupts for TINT selection is 141
> >    instead of 86.
> >  - The pin index and TINT selection index are not in the 1:1 map
> >  - The number of TSSR registers is 15 instead of 8

Will fix the typo 15->16 as you mentioned later.

Cheers,
Biju
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
index d7ef4f1323a7..3f99c8645767 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
@@ -4,7 +4,7 @@ 
 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/V2H(P) Interrupt Control Unit
+title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit
 
 maintainers:
   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
@@ -20,7 +20,9 @@  description:
 
 properties:
   compatible:
-    const: renesas,r9a09g057-icu # RZ/V2H(P)
+    enum:
+      - renesas,r9a09g047-icu # RZ/G3E
+      - renesas,r9a09g057-icu # RZ/V2H(P)
 
   '#interrupt-cells':
     description: The first cell is the SPI number of the NMI or the