| Message ID | 20250207113653.21641-11-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Support for RZ/G3E ICU | expand |
On 2/7/25 2:36 PM, Biju Das wrote: > On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. > Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved > bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs > for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and > ICU_TSSR_TSSEL_MASK. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> [...] > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c > index 6d1de9277c7d..71d06820e598 100644 > --- a/drivers/irqchip/irq-renesas-rzv2h.c > +++ b/drivers/irqchip/irq-renesas-rzv2h.c [...] > @@ -321,8 +318,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > guard(raw_spinlock)(&priv->lock); > > tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); > - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); > - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); > + tssr &= ~((GENMASK(priv->info->field_width - 2, 0) << > + (tssel_n * priv->info->field_width)) | tien); > + tssr |= (tint << (tssel_n * priv->info->field_width)); Don't need () around the |='s rvalue. [...] MBR, Sergey
On Fri, 7 Feb 2025 at 12:37, Biju Das <biju.das.jz@bp.renesas.com> wrote: > On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. > Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved > bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs > for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and > ICU_TSSR_TSSEL_MASK. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> For the logical change: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hi Sergey, Thanks for the feedback. > -----Original Message----- > From: Sergey Shtylyov <s.shtylyov@omp.ru> > Sent: 07 February 2025 13:53 > Subject: Re: [PATCH v4 10/12] irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP} > > On 2/7/25 2:36 PM, Biju Das wrote: > > > On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. > > Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved > > bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both > > SoCs for extracting TSSEL and we can drop the macros > > ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > [...] > > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c > > b/drivers/irqchip/irq-renesas-rzv2h.c > > index 6d1de9277c7d..71d06820e598 100644 > > --- a/drivers/irqchip/irq-renesas-rzv2h.c > > +++ b/drivers/irqchip/irq-renesas-rzv2h.c > [...] > > @@ -321,8 +318,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > > guard(raw_spinlock)(&priv->lock); > > > > tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); > > - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); > > - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); > > + tssr &= ~((GENMASK(priv->info->field_width - 2, 0) << > > + (tssel_n * priv->info->field_width)) | tien); > > + tssr |= (tint << (tssel_n * priv->info->field_width)); > > Don't need () around the |='s rvalue. Agree. Will fix this in next version. Cheers, Biju
diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 6d1de9277c7d..71d06820e598 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,9 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) - #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) @@ -321,8 +318,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); + tssr &= ~((GENMASK(priv->info->field_width - 2, 0) << + (tssel_n * priv->info->field_width)) | tien); + tssr |= (tint << (tssel_n * priv->info->field_width)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v4: * New patch --- drivers/irqchip/irq-renesas-rzv2h.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)