From patchwork Wed Feb 12 11:12:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13971382 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A026E20A5C9 for ; Wed, 12 Feb 2025 11:13:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739358789; cv=none; b=aEaGLSQE6zhNBa30bfyD2nLsL4xuvtmZw5avhpRzqYuo3c8wPMe+A+HFGWW2KpQkHNAW3bd5yzmVdDMQVWhjhyBFXBjSIxP8q9ANEaHDXveZr84Ekag/vF6gKRug6ESBBwv3IIQWRdNJZbPAMR+T6d/3PFp39xatDMuHCjZMDVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739358789; c=relaxed/simple; bh=kJkDDsUd12fBfDWwCi69kAFrZgFMKkGtLlcF2mgzOME=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vb6NrVFuivh//Tw+BDieowF5H0iMNvQK+n8/pSX3fz8J+KMutxhwsjXqwRVEnQ9K9LAF8TqpgjFtBwQxaNtrEnhnl2AjIAc1ZYtsmBYwOLwpwFeNVHEZ/pNUJImE6uvheCaevpnlgWRIkBA1iA5fXe9JrLfYsQH+ImouWaPBdRs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: /lkEHWzhSbKj4kFCueFRIA== X-CSE-MsgGUID: Zgw71jb9R9eoHtasv750pg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 12 Feb 2025 20:13:06 +0900 Received: from localhost.localdomain (unknown [10.226.92.135]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B71D9425CA29; Wed, 12 Feb 2025 20:13:04 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro Date: Wed, 12 Feb 2025 11:12:19 +0000 Message-ID: <20250212111231.143277-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212111231.143277-1-biju.das.jz@bp.renesas.com> References: <20250212111231.143277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The macro ICU_TSSR_TIEN(n) can be replaced with the inline logic BIT(field_width - 1) << (n * fieldwidth) for supporting both SoCs. Signed-off-by: Biju Das --- v4->v5: * Shortened tssr calculation in rzv2h_tint_irq_endisable(). * Added tssr_shift_factor variable for optimizing the calculation in rzv2h_tint_set_type() as the next patch uses the same factor. v4: * New patch --- drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 98a6a7cd3611..3635597ae4c1 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -66,7 +66,6 @@ #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) @@ -153,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) - tssr |= ICU_TSSR_TIEN(tssel_n); + tssr |= BIT((tssel_n + 1) * priv->info->field_width - 1); else - tssr &= ~ICU_TSSR_TIEN(tssel_n); + tssr &= ~(BIT((tssel_n + 1) * priv->info->field_width - 1)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } @@ -277,6 +276,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) u32 titsr, titsr_k, titsel_n, tien; struct rzv2h_icu_priv *priv; u32 tssr, tssr_k, tssel_n; + u32 tssr_shift_factor; unsigned int hwirq; u32 tint, sense; int tint_nr; @@ -314,7 +314,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) nr_tint = 32 / priv->info->field_width; tssr_k = tint_nr / nr_tint; tssel_n = tint_nr % nr_tint; - tien = ICU_TSSR_TIEN(tssel_n); + tssr_shift_factor = tssel_n * priv->info->field_width; + tien = BIT(priv->info->field_width - 1) << tssr_shift_factor; titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr);