From patchwork Wed Feb 12 11:12:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13971383 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0E02F20A5E9 for ; Wed, 12 Feb 2025 11:13:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739358791; cv=none; b=AzP/zWNstWFLZxbXWmGdSATww2v6xwGmynjJ2VXyfjyIYw084yRqlPU67lGAwQ4IxrTb8Ky23R0WyMmDStZ0AbpNpiYSOy9MIRowV4opRXAAvRqW3arwpMqH2EZe/+ZuhNMbUp84ygLGuLoHUksXc72dwIKvUz/WIg7pflXkqJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739358791; c=relaxed/simple; bh=DVlz5uow6T9iud/2pWR5OpA+vOYN1g8zZ4SaS3P7Sq0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=poXhxOvC78hEXQ4+jnV5eB6HoQaB7BrPA/lp35lDbIkEqxQh3yKWoJP++JcwJjX/kadPBysCwilXGUis2EyUr62MLXEIIXJUPxHHW72Ij3F3sHjWczjZ/n9sCl+WKX8nNd5AAP9MIOQKzWJozf72Jqo9LglMNEDGFQttxIaZugs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: HdW+BMfmSf+ASrkRt0C5sw== X-CSE-MsgGUID: RsHPoKOORGq3JGON6NPqJw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 12 Feb 2025 20:13:09 +0900 Received: from localhost.localdomain (unknown [10.226.92.135]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 32EC3425CA23; Wed, 12 Feb 2025 20:13:06 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v5 11/12] irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP} Date: Wed, 12 Feb 2025 11:12:20 +0000 Message-ID: <20250212111231.143277-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212111231.143277-1-biju.das.jz@bp.renesas.com> References: <20250212111231.143277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v4->v5: * Used tssr_shift_factor in rzv2h_tint_set_type to optimize the calculation. * Dropped unnecessary parenthesis for calculating tssr. * Added Rb tag from Geert. v4: * New patch --- drivers/irqchip/irq-renesas-rzv2h.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 3635597ae4c1..6cfa7f663ce0 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,9 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) - #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) @@ -323,8 +320,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); + tssr &= ~((GENMASK(priv->info->field_width - 2, 0) << tssr_shift_factor) | tien); + tssr |= tint << tssr_shift_factor; writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));