@@ -10,6 +10,8 @@
/* Switch selection settings */
#define SW_SD0_DEV_SEL 0
#define SW_SDIO_M2E 0
+#define SW_GPIO8_CAN0_STB 0
+#define SW_GPIO9_CAN1_STB 0
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
@@ -33,7 +35,50 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
};
};
+&canfd {
+ pinctrl-0 = <&canfd_pins>;
+ pinctrl-names = "default";
+
+ channel1 {
+ status = "okay";
+ };
+
+ channel4 {
+ status = "okay";
+ };
+};
+
&pinctrl {
+#if SW_GPIO8_CAN0_STB
+ can0-stb-hog {
+ gpio-hog;
+ gpios = <RZG3E_GPIO(5, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can0_stb";
+ };
+#endif
+
+#if SW_GPIO9_CAN1_STB
+ can1-stb-hog {
+ gpio-hog;
+ gpios = <RZG3E_GPIO(5, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can1_stb";
+ };
+#endif
+
+ canfd_pins: canfd {
+ can1_pins: can1 {
+ pinmux = <RZG3E_PORT_PINMUX(L, 2, 3)>, /* RX */
+ <RZG3E_PORT_PINMUX(L, 3, 3)>; /* TX */
+ };
+
+ can4_pins: can4 {
+ pinmux = <RZG3E_PORT_PINMUX(5, 2, 3)>, /* RX */
+ <RZG3E_PORT_PINMUX(5, 3, 3)>; /* TX */
+ };
+ };
+
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;
@@ -12,6 +12,17 @@
* SW_SDIO_M2E:
* 0 - SMARC SDIO signal is connected to uSD1
* 1 - SMARC SDIO signal is connected to M.2 Key E connector
+ *
+ * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the
+ * corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS:
+ *
+ * SW_GPIO8_CAN0_STB:
+ * 0 - Connect to GPIO8 PMOD (default)
+ * 1 - Connect to CAN0 transceiver STB pin
+ *
+ * SW_GPIO9_CAN1_STB:
+ * 0 - Connect to GPIO9 PMOD (default)
+ * 1 - Connect to CAN1 transceiver STB pin
*/
/ {
@@ -29,6 +40,10 @@ aliases {
};
};
+&canfd {
+ status = "okay";
+};
+
&scif0 {
status = "okay";
};
Enable CANFD on the RZ/G3E SMARC EVK platform. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 45 +++++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 15 +++++++ 2 files changed, 60 insertions(+)