From patchwork Thu Feb 20 15:26:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13984138 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0BD921FDE06; Thu, 20 Feb 2025 15:27:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740065272; cv=none; b=g+huqd/Q2ue9xTD98n70QeKOrI10D69jWYutRLPiAslUaRqa9sAN2DczA06sk2CvZ/ora/y7a2hlp3YuwEYM7CDJeXZja9BlxcolvAljDKKcL8atYzFcib1qt2yXh/IT2SaLC85sxplRZDoDXnBFH0x2rU5Z2K/IC8UyhgxQZN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740065272; c=relaxed/simple; bh=rXnobFmrvMmMBwc7ssyoFJQ3Uz7vfCbIQpjOoOpSmXE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g+EQrQtHMyKzDHsoj7ItM4SwHrLmquYcFW66KugpdyQuJV6NeDNrN8Nsb2MjIxerkKYvhv1XkEuKR2a+5JaTom6J+yY+DiLlr5AkbCDDJ49A/oK6W1vC9hudl/SI3CWDxspxeKVaiaMBz5awwGWocO9Eq8KPoOAn2QJKHkzQwC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ipAMMgacQB6VhWLVMse7Cw== X-CSE-MsgGUID: fvaJLnYeQV2q0VUFDfLJAg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 21 Feb 2025 00:27:49 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.134]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0CED040436EB; Fri, 21 Feb 2025 00:27:43 +0900 (JST) From: John Madieu To: mturquette@baylibre.com, magnus.damm@gmail.com, krzk+dt@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, sboyd@kernel.org, geert+renesas@glider.be, lukasz.luba@arm.com, rafael@kernel.org, robh@kernel.org, p.zabel@pengutronix.de Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, John Madieu Subject: [PATCH 2/7] clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP Date: Thu, 20 Feb 2025 16:26:07 +0100 Message-ID: <20250220152640.49010-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250220152640.49010-1-john.madieu.xa@bp.renesas.com> References: <20250220152640.49010-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add required clocks and resets signals for the TSU IP available on the Renesas RZ/G3E SoC Signed-off-by: John Madieu --- drivers/clk/renesas/r9a09g047-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 51fd24c20ed5..ada57964c132 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -154,6 +154,8 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(8, BIT(4))), DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, BUS_MSTOP(8, BIT(4))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { @@ -177,6 +179,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {