| Message ID | 20250224131253.134199-11-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Support for RZ/G3E ICU | expand |
On Mon, 24 Feb 2025 at 14:13, Biju Das <biju.das.jz@bp.renesas.com> wrote: > On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. Replace the > macro ICU_TSSR_TIEN(n)->ICU_TSSR_TIEN(n, _field_width) for supporting both > these SoCs. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v5->v6: > * Retained the macro ICU_TSSR_TIEN by adding _field_width parameter. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hi Thomas, Sending the patch with both commit description and ICU_TSSR_TIEN macro updated with _field_width->field_width. Cheers, Biju > -----Original Message----- > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: 24 February 2025 13:46 > To: Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [PATCH v6 10/12] irqchip/renesas-rzv2h: Update TSSR_TIEN macro > > On Mon, 24 Feb 2025 at 14:13, Biju Das <biju.das.jz@bp.renesas.com> wrote: > > On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. Replace > > the macro ICU_TSSR_TIEN(n)->ICU_TSSR_TIEN(n, field_width) for > > supporting both these SoCs. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v5->v6: > > * Retained the macro ICU_TSSR_TIEN by adding _field_width parameter. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 98a6a7cd3611..8d0bd4d69de2 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -66,7 +66,11 @@ #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) +#define ICU_TSSR_TIEN(n, field_width) \ +({\ + typeof(field_width) (_field_width) = (field_width); \ + BIT((_field_width) - 1) << ((n) * (_field_width)); \ +}) #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) @@ -153,9 +157,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) - tssr |= ICU_TSSR_TIEN(tssel_n); + tssr |= ICU_TSSR_TIEN(tssel_n, priv->info->field_width); else - tssr &= ~ICU_TSSR_TIEN(tssel_n); + tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } @@ -314,7 +318,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) nr_tint = 32 / priv->info->field_width; tssr_k = tint_nr / nr_tint; tssel_n = tint_nr % nr_tint; - tien = ICU_TSSR_TIEN(tssel_n); + tien = ICU_TSSR_TIEN(tssel_n, priv->info->field_width); titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 98a6a7cd3611..ac71ce9810f8 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -66,7 +66,11 @@ #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) +#define ICU_TSSR_TIEN(n, _field_width) \ +({\ + typeof(_field_width) (field_width) = (_field_width); \ + BIT((field_width) - 1) << ((n) * (field_width)); \ +}) #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) @@ -153,9 +157,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) - tssr |= ICU_TSSR_TIEN(tssel_n); + tssr |= ICU_TSSR_TIEN(tssel_n, priv->info->field_width); else - tssr &= ~ICU_TSSR_TIEN(tssel_n); + tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } @@ -314,7 +318,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) nr_tint = 32 / priv->info->field_width; tssr_k = tint_nr / nr_tint; tssel_n = tint_nr % nr_tint; - tien = ICU_TSSR_TIEN(tssel_n); + tien = ICU_TSSR_TIEN(tssel_n, priv->info->field_width); titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. Replace the macro ICU_TSSR_TIEN(n)->ICU_TSSR_TIEN(n, _field_width) for supporting both these SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v5->v6: * Retained the macro ICU_TSSR_TIEN by adding _field_width parameter. v4->v5: * Shortened tssr calculation in rzv2h_tint_irq_endisable(). * Added tssr_shift_factor variable for optimizing the calculation in rzv2h_tint_set_type() as the next patch uses the same factor. v4: * New patch --- drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)