diff mbox series

[v3,07/11] can: rcar_canfd: Add mask table to struct rcar_canfd_hw_info

Message ID 20250225154058.59116-8-biju.das.jz@bp.renesas.com (mailing list archive)
State New
Delegated to: Geert Uytterhoeven
Headers show
Series Add support for RZ/G3E CANFD | expand

Commit Message

Biju Das Feb. 25, 2025, 3:40 p.m. UTC 
R-Car Gen3 and Gen4 has some differences in the mask bits. Add a
mask table to handle these differences.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3:
 * New patch.
---
 drivers/net/can/rcar/rcar_canfd.c | 68 +++++++++++++++++++++++++------
 1 file changed, 55 insertions(+), 13 deletions(-)

Comments

Marc Kleine-Budde Feb. 25, 2025, 3:49 p.m. UTC | #1 
On 25.02.2025 15:40:46, Biju Das wrote:
> R-Car Gen3 and Gen4 has some differences in the mask bits. Add a
> mask table to handle these differences.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3:
>  * New patch.
> ---
>  drivers/net/can/rcar/rcar_canfd.c | 68 +++++++++++++++++++++++++------
>  1 file changed, 55 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
> index 268b9b8835c4..fcf5cb93f57c 100644
> --- a/drivers/net/can/rcar/rcar_canfd.c
> +++ b/drivers/net/can/rcar/rcar_canfd.c

> +enum rcar_canfd_mask_id {
> +	EEF_MASK_ID,	/* Global Error Flag */
> +	RNC_MASK_ID,	/* Rule Number for Channel */
> +	AFLPN_MASK_ID,	/* Acceptance Filter List Page Number */
> +	NTSEG2_MASK_ID,	/* Nominal Bit Rate Time Segment 2 Control */
> +	NTSEG1_MASK_ID,	/* Nominal Bit Rate Time Segment 1 Control */
> +	NSJW_MASK_ID,	/* Nominal Bit Rate Resynchronization Jump Width Control */
> +	DSJW_MASK_ID,	/* Data Bit Rate Resynchronization Jump Width Control */
> +	DTSEG2_MASK_ID,	/* Data Bit Rate Time Segment 2 Control */
> +	DTSEG1_MASK_ID,	/* Data Bit Rate Time Segment 1 Control */
> +	CFTML_MASK_ID,	/* Common FIFO TX Message Buffer Link */
> +};

Please add a common prefix to the enums, i.e. RCANFD_.

Marc
diff mbox series

Patch

diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index 268b9b8835c4..fcf5cb93f57c 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -82,25 +82,24 @@ 
 #define RCANFD_GERFL_DEF		BIT(0)
 
 #define RCANFD_GERFL_ERR(gpriv, x) \
-	((x) & (reg_gen4(gpriv, RCANFD_GERFL_EEF0_7, \
-			 RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1)) | \
-		RCANFD_GERFL_MES | \
+	((x) & ((gpriv)->info->mask_table[EEF_MASK_ID] | RCANFD_GERFL_MES | \
 		((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
 
 /* AFL Rx rules registers */
 
 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
 #define RCANFD_GAFLCFG_SETRNC(gpriv, n, x) \
-	(((x) & reg_gen4(gpriv, 0x1ff, 0xff)) << \
+	(((x) & (gpriv)->info->mask_table[RNC_MASK_ID]) << \
 	 (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8)))
 
 #define RCANFD_GAFLCFG_GETRNC(gpriv, n, x) \
 	(((x) >> (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8))) & \
-	 reg_gen4(gpriv, 0x1ff, 0xff))
+	 (gpriv)->info->mask_table[RNC_MASK_ID])
 
 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 #define RCANFD_GAFLECTR_AFLDAE		BIT(8)
-#define RCANFD_GAFLECTR_AFLPN(gpriv, x)	((x) & reg_gen4(gpriv, 0x7f, 0x1f))
+#define RCANFD_GAFLECTR_AFLPN(gpriv, x)	((x) & \
+					 (gpriv)->info->mask_table[AFLPN_MASK_ID])
 
 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 #define RCANFD_GAFLID_GAFLLB		BIT(29)
@@ -118,13 +117,13 @@ 
 
 /* RSCFDnCFDCmNCFG - CAN FD only */
 #define RCANFD_NCFG_NTSEG2(gpriv, x) \
-	(((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 25, 24))
+	(((x) & (gpriv)->info->mask_table[NTSEG2_MASK_ID]) << reg_gen4(gpriv, 25, 24))
 
 #define RCANFD_NCFG_NTSEG1(gpriv, x) \
-	(((x) & reg_gen4(gpriv, 0xff, 0x7f)) << reg_gen4(gpriv, 17, 16))
+	(((x) & (gpriv)->info->mask_table[NTSEG1_MASK_ID]) << reg_gen4(gpriv, 17, 16))
 
 #define RCANFD_NCFG_NSJW(gpriv, x) \
-	(((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 10, 11))
+	(((x) & (gpriv)->info->mask_table[NSJW_MASK_ID]) << reg_gen4(gpriv, 10, 11))
 
 #define RCANFD_NCFG_NBRP(x)		(((x) & 0x3ff) << 0)
 
@@ -186,13 +185,13 @@ 
 #define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
 
 /* RSCFDnCFDCmDCFG */
-#define RCANFD_DCFG_DSJW(gpriv, x)	(((x) & reg_gen4(gpriv, 0xf, 0x7)) << 24)
+#define RCANFD_DCFG_DSJW(gpriv, x)	(((x) & (gpriv)->info->mask_table[DSJW_MASK_ID]) << 24)
 
 #define RCANFD_DCFG_DTSEG2(gpriv, x) \
-	(((x) & reg_gen4(gpriv, 0x0f, 0x7)) << reg_gen4(gpriv, 16, 20))
+	(((x) & (gpriv)->info->mask_table[DTSEG2_MASK_ID]) << reg_gen4(gpriv, 16, 20))
 
 #define RCANFD_DCFG_DTSEG1(gpriv, x) \
-	(((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 8, 16))
+	(((x) & (gpriv)->info->mask_table[DTSEG1_MASK_ID]) << reg_gen4(gpriv, 8, 16))
 
 #define RCANFD_DCFG_DBRP(x)		(((x) & 0xff) << 0)
 
@@ -234,7 +233,7 @@ 
 
 /* RSCFDnCFDCFCCk */
 #define RCANFD_CFCC_CFTML(gpriv, x)	\
-	(((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 16, 20))
+	(((x) & (gpriv)->info->mask_table[CFTML_MASK_ID]) << reg_gen4(gpriv, 16, 20))
 #define RCANFD_CFCC_CFM(gpriv, x)	(((x) & 0x3) << reg_gen4(gpriv,  8, 16))
 #define RCANFD_CFCC_CFIM		BIT(12)
 #define RCANFD_CFCC_CFDC(gpriv, x)	(((x) & 0x7) << reg_gen4(gpriv, 21,  8))
@@ -518,9 +517,23 @@  enum rcar_canfd_reg_offset_id {
 	CFOFFSET,	/* Transmit/receive FIFO buffer access ID register */
 };
 
+enum rcar_canfd_mask_id {
+	EEF_MASK_ID,	/* Global Error Flag */
+	RNC_MASK_ID,	/* Rule Number for Channel */
+	AFLPN_MASK_ID,	/* Acceptance Filter List Page Number */
+	NTSEG2_MASK_ID,	/* Nominal Bit Rate Time Segment 2 Control */
+	NTSEG1_MASK_ID,	/* Nominal Bit Rate Time Segment 1 Control */
+	NSJW_MASK_ID,	/* Nominal Bit Rate Resynchronization Jump Width Control */
+	DSJW_MASK_ID,	/* Data Bit Rate Resynchronization Jump Width Control */
+	DTSEG2_MASK_ID,	/* Data Bit Rate Time Segment 2 Control */
+	DTSEG1_MASK_ID,	/* Data Bit Rate Time Segment 1 Control */
+	CFTML_MASK_ID,	/* Common FIFO TX Message Buffer Link */
+};
+
 struct rcar_canfd_global;
 
 struct rcar_canfd_hw_info {
+	const u32 *mask_table;
 	const u16 *regs;
 	u8 max_channels;
 	u8 postdiv;
@@ -619,7 +632,34 @@  static const u16 rcar_gen4_regs[] = {
 	[CFOFFSET] = 0x6400,
 };
 
+static const u32 rcar_gen3_mask_table[] = {
+	[EEF_MASK_ID] = RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1),
+	[RNC_MASK_ID] = 0xff,
+	[AFLPN_MASK_ID] = 0x1f,
+	[NTSEG2_MASK_ID] = 0x1f,
+	[NTSEG1_MASK_ID] = 0x7f,
+	[NSJW_MASK_ID] = 0x1f,
+	[DSJW_MASK_ID] = 0x7,
+	[DTSEG2_MASK_ID] = 0x7,
+	[DTSEG1_MASK_ID] = 0xf,
+	[CFTML_MASK_ID] = 0xf,
+};
+
+static const u32 rcar_gen4_mask_table[] = {
+	[EEF_MASK_ID] = RCANFD_GERFL_EEF0_7,
+	[RNC_MASK_ID] = 0x1ff,
+	[AFLPN_MASK_ID] = 0x7f,
+	[NTSEG2_MASK_ID] = 0x7f,
+	[NTSEG1_MASK_ID] = 0xff,
+	[NSJW_MASK_ID] = 0x7f,
+	[DSJW_MASK_ID] = 0xf,
+	[DTSEG2_MASK_ID] = 0xf,
+	[DTSEG1_MASK_ID] = 0x1f,
+	[CFTML_MASK_ID] = 0x1f,
+};
+
 static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
+	.mask_table = rcar_gen3_mask_table,
 	.regs = rcar_gen3_regs,
 	.max_channels = 2,
 	.postdiv = 2,
@@ -627,6 +667,7 @@  static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
 };
 
 static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
+	.mask_table = rcar_gen4_mask_table,
 	.regs = rcar_gen4_regs,
 	.max_channels = 8,
 	.postdiv = 2,
@@ -636,6 +677,7 @@  static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
 };
 
 static const struct rcar_canfd_hw_info rzg2l_hw_info = {
+	.mask_table = rcar_gen3_mask_table,
 	.regs = rcar_gen3_regs,
 	.max_channels = 2,
 	.postdiv = 1,