| Message ID | 20250330195715.332106-2-marek.vasut+renesas@mailbox.org (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: r8a779g3: Add Renesas R-Car V4H Sparrow Hawk board support | expand |
On Sun, Mar 30, 2025 at 09:56:09PM +0200, Marek Vasut wrote: > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml > index bb3f843c59d91..5e2624d4c62c7 100644 > --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml > @@ -46,12 +46,14 @@ properties: > - const: app > > clocks: > - maxItems: 2 > + minItems: 2 > + maxItems: 3 > > clock-names: missing minItems: 2 (xxx and xxx-names are always synced in dimensions) I understand that clock is optional? Your diagram in commit msg suggests that clock is there always. Best regards, Krzysztof
On 3/31/25 10:19 AM, Krzysztof Kozlowski wrote: > On Sun, Mar 30, 2025 at 09:56:09PM +0200, Marek Vasut wrote: >> diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml >> index bb3f843c59d91..5e2624d4c62c7 100644 >> --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml >> +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml >> @@ -46,12 +46,14 @@ properties: >> - const: app >> >> clocks: >> - maxItems: 2 >> + minItems: 2 >> + maxItems: 3 >> >> clock-names: > > missing minItems: 2 > > (xxx and xxx-names are always synced in dimensions) Fixed, noted, thanks ! > I understand that clock is optional? Your diagram in commit msg suggests > that clock is there always. The clocks which supply the PCIe controller ("ref" clock) and PCIe bus ("aux" clock) can be modeled as either, single clock (one clock for both controller AND bus, i.e. single "ref" clock), or two separate clocks (one for controller AND one for bus, i.e. "ref" clock AND "aux" clock). That depends on whether the clock generator (the 9FGV0441 brick in the ASCII schematic in the commit message in this case) has one flip switch to enable both clock (controller and bus, i.e. "ref" clock only), or has separate flip switches to enable the different outputs (controller or bus, i.e. "ref" and "aux" clock). So yes, the "aux" is optional from the software side, but on the hardware side, the "aux" bus clock are always there. They however do not always have separate flip switch to enable/disable them.
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index bb3f843c59d91..5e2624d4c62c7 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -46,12 +46,14 @@ properties: - const: app clocks: - maxItems: 2 + minItems: 2 + maxItems: 3 clock-names: items: - const: core - const: ref + - const: aux power-domains: maxItems: 1 @@ -105,8 +107,8 @@ examples: <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi", "dma", "sft_ce", "app"; - clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; - clock-names = "core", "ref"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>, <&pcie0_clkgen>; + clock-names = "core", "ref", "aux"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 624>; reset-names = "pwr";
Document 'aux' clock which are used to supply the PCIe bus. This is useful in case of a hardware setup, where the PCIe controller input clock and the PCIe bus clock are supplied from the same clock synthesiser, but from different differential clock outputs: ____________ _____________ | R-Car PCIe | | PCIe device | | | | | | PCIe RX<|==================|>PCIe TX | | PCIe TX<|==================|>PCIe RX | | | | | | PCIe CLK<|======.. ..======|>PCIe CLK | '------------' || || '-------------' || || ____________ || || | 9FGV0441 | || || | | || || | CLK DIF0<|======'' || | CLK DIF1<|=========='' | CLK DIF2<| | CLK DIF3<| '------------' The clock are named 'aux' because those are one of the clock listed in Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which fit closest to the PCIe bus clock. According to that binding document, the 'aux' clock describe clock which supply the PMC domain, which is likely PCIe Mezzanine Card domain. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml instead and add 'bus' clock outright ? --- Cc: "Krzysztof Wilczyński" <kw@linux.com> Cc: "Rafał Miłecki" <rafal@milecki.pl> Cc: Aradhya Bhatia <a-bhatia1@ti.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Junhao Xie <bigfoot@classfun.cn> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- .../devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)