[11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support

Commit Message

Prabhakar March 30, 2025, 9:07 p.m. UTC

From: Lad Prabhakar <[e-mail]>

In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding configurations.

The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to the one
on the RZ/G2L SoC. While the LINK registers are shared between the two
SoCs, the D-PHY registers differ. Also the VCLK range differs on both these
SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` is
introduced and as now passed as OF data.

These changes lay the groundwork for the upcoming RZ/V2H(P) SoC support by
allowing SoC-specific data to be passed through OF.

Co-developed-by: Fabrizio Castro <[e-mail]>
Signed-off-by: Fabrizio Castro <[e-mail]>
Signed-off-by: Lad Prabhakar <[e-mail]>
---
 .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c    | 66 ++++++++++++++-----
 .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h   |  2 -
 2 files changed, 49 insertions(+), 19 deletions(-)

Comments

Biju Das March 31, 2025, 12:38 p.m. UTC | #1

Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <[e-mail]>
> Sent: 30 March 2025 22:07
> Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support
> 
> From: Lad Prabhakar <[e-mail]>
> 
> In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to
> pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt
> dynamically to various SoC-specific requirements without hardcoding configurations.
> 
> The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to the one on the RZ/G2L SoC. While
> the LINK registers are shared between the two SoCs, the D-PHY registers differ. Also the VCLK range
> differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` is
> introduced and as now passed as OF data.
> 
> These changes lay the groundwork for the upcoming RZ/V2H(P) SoC support by allowing SoC-specific data
> to be passed through OF.
> 
> Co-developed-by: Fabrizio Castro <[e-mail]>
> Signed-off-by: Fabrizio Castro <[e-mail]>
> Signed-off-by: Lad Prabhakar <[e-mail]>
> ---
>  .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c    | 66 ++++++++++++++-----
>  .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h   |  2 -
>  2 files changed, 49 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-
> du/rzg2l_mipi_dsi.c
> index e0379f099659..44b95082b29c 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -28,10 +28,24 @@
> 
>  #include "rzg2l_mipi_dsi_regs.h"
> 
> +struct rzg2l_mipi_dsi;
> +
> +struct rzg2l_mipi_dsi_hw_info {
> +	int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq);
> +	void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
> +	u32 phy_reg_offset;
> +	u32 link_reg_offset;
> +	unsigned long max_dclk;
> +	unsigned long min_dclk;
> +	bool has_dphy_rstc;
> +};
> +
>  struct rzg2l_mipi_dsi {
>  	struct device *dev;
>  	void __iomem *mmio;
> 
> +	const struct rzg2l_mipi_dsi_hw_info *info;
> +
>  	struct reset_control *rstc;
>  	struct reset_control *arstc;
>  	struct reset_control *prstc;
> @@ -164,22 +178,22 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = {
> 
>  static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)  {
> -	iowrite32(data, dsi->mmio + reg);
> +	iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg);
>  }
> 
>  static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)  {
> -	iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg);
> +	iowrite32(data, dsi->mmio + dsi->info->link_reg_offset + reg);
>  }
> 
>  static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg)  {
> -	return ioread32(dsi->mmio + reg);
> +	return ioread32(dsi->mmio + dsi->info->phy_reg_offset + reg);
>  }
> 
>  static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)  {
> -	return ioread32(dsi->mmio + LINK_REG_OFFSET + reg);
> +	return ioread32(dsi->mmio + dsi->info->link_reg_offset + reg);
>  }
> 
>  /* -----------------------------------------------------------------------------
> @@ -291,7 +305,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
>  	vclk_rate = clk_get_rate(dsi->vclk);
>  	hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes);
> 
> -	ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq);
> +	ret = dsi->info->dphy_init(dsi, hsfreq);
>  	if (ret < 0)
>  		goto err_phy;
> 
> @@ -334,7 +348,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
>  	return 0;
> 
>  err_phy:
> -	rzg2l_mipi_dsi_dphy_exit(dsi);
> +	dsi->info->dphy_exit(dsi);
>  	pm_runtime_put(dsi->dev);
> 
>  	return ret;
> @@ -342,7 +356,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
> 
>  static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi)  {
> -	rzg2l_mipi_dsi_dphy_exit(dsi);
> +	dsi->info->dphy_exit(dsi);
>  	pm_runtime_put(dsi->dev);
>  }
> 
> @@ -585,10 +599,12 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
>  				 const struct drm_display_info *info,
>  				 const struct drm_display_mode *mode)  {
> -	if (mode->clock > 148500)
> +	struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
> +
> +	if (mode->clock > dsi->info->max_dclk)
>  		return MODE_CLOCK_HIGH;
> 
> -	if (mode->clock < 5803)
> +	if (mode->clock < dsi->info->min_dclk)
>  		return MODE_CLOCK_LOW;
> 
>  	return MODE_OK;
> @@ -714,6 +730,11 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>  	platform_set_drvdata(pdev, dsi);
>  	dsi->dev = &pdev->dev;
> 
> +	dsi->info = of_device_get_match_data(&pdev->dev);
> +	if (!dsi->info)
> +		return dev_err_probe(dsi->dev, -ENODEV,
> +				     "missing data info\n");
> +
>  	ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
>  	if (ret < 0)
>  		return dev_err_probe(dsi->dev, ret,
> @@ -729,10 +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>  	if (IS_ERR(dsi->vclk))
>  		return PTR_ERR(dsi->vclk);
> 
> -	dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
> -	if (IS_ERR(dsi->rstc))
> -		return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> -				     "failed to get rst\n");
> +	if (dsi->info->has_dphy_rstc) {
> +		dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");

Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc.

Cheers,
Biju

> +		if (IS_ERR(dsi->rstc))
> +			return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> +					     "failed to get rst\n");
> +	}
> 
>  	dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst");
>  	if (IS_ERR(dsi->arstc))
> @@ -757,13 +780,13 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>  	 * mode->clock and format are not available. So initialize DPHY with
>  	 * timing parameters for 80Mbps.
>  	 */
> -	ret = rzg2l_mipi_dsi_dphy_init(dsi, 80000000);
> +	ret = dsi->info->dphy_init(dsi, 80000000);
>  	if (ret < 0)
>  		goto err_phy;
> 
>  	txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR);
>  	dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes);
> -	rzg2l_mipi_dsi_dphy_exit(dsi);
> +	dsi->info->dphy_exit(dsi);
>  	pm_runtime_put(dsi->dev);
> 
>  	/* Initialize the DRM bridge. */
> @@ -780,7 +803,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>  	return 0;
> 
>  err_phy:
> -	rzg2l_mipi_dsi_dphy_exit(dsi);
> +	dsi->info->dphy_exit(dsi);
>  	pm_runtime_put(dsi->dev);
>  err_pm_disable:
>  	pm_runtime_disable(dsi->dev);
> @@ -795,8 +818,17 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev)
>  	pm_runtime_disable(&pdev->dev);
>  }
> 
> +static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = {
> +	.dphy_init = rzg2l_mipi_dsi_dphy_init,
> +	.dphy_exit = rzg2l_mipi_dsi_dphy_exit,
> +	.has_dphy_rstc = true,
> +	.link_reg_offset = 0x10000,
> +	.max_dclk = 148500,
> +	.min_dclk = 5803,
> +};
> +
>  static const struct of_device_id rzg2l_mipi_dsi_of_table[] = {
> -	{ .compatible = "renesas,rzg2l-mipi-dsi" },
> +	{ .compatible = "renesas,rzg2l-mipi-dsi", .data =
> +&rzg2l_mipi_dsi_info, },
>  	{ /* sentinel */ }
>  };
> 
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-
> du/rzg2l_mipi_dsi_regs.h
> index 1dbc16ec64a4..16efe4dc59f4 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> @@ -41,8 +41,6 @@
>  #define DSIDPHYTIM3_THS_ZERO(x)		((x) << 0)
> 
>  /* --------------------------------------------------------*/
> -/* Link Registers */
> -#define LINK_REG_OFFSET			0x10000
> 
>  /* Link Status Register */
>  #define LINKSR				0x10
> --
> 2.49.0

Prabhakar March 31, 2025, 1:58 p.m. UTC | #2

Hi Biju,

Thank you for the review.

On Mon, Mar 31, 2025 at 1:38 PM Biju Das <[e-mail]> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <[e-mail]>
> > Sent: 30 March 2025 22:07
> > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support
> >
> > From: Lad Prabhakar <[e-mail]>
> >
> > In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to
> > pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt
> > dynamically to various SoC-specific requirements without hardcoding configurations.
> >
> > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to the one on the RZ/G2L SoC. While
> > the LINK registers are shared between the two SoCs, the D-PHY registers differ. Also the VCLK range
> > differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` is
> > introduced and as now passed as OF data.
> >
> > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC support by allowing SoC-specific data
> > to be passed through OF.
> >
<snip>
> > +
> >       ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
> >       if (ret < 0)
> >               return dev_err_probe(dsi->dev, ret,
> > @@ -729,10 +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> >       if (IS_ERR(dsi->vclk))
> >               return PTR_ERR(dsi->vclk);
> >
> > -     dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
> > -     if (IS_ERR(dsi->rstc))
> > -             return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> > -                                  "failed to get rst\n");
> > +     if (dsi->info->has_dphy_rstc) {
> > +             dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
>
> Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc.
>
As the dtbs_check doesn't enforce this,  `has_dphy_rstc` flag was
added. Recently the same was done for the CRU [0] based on the recent
comment received.

[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[e-mail]/

Cheers,
Prabhakar

Biju Das March 31, 2025, 2:14 p.m. UTC | #3

> -----Original Message-----
> From: Lad, Prabhakar <[e-mail]>
> Sent: 31 March 2025 14:59
> To: Biju Das <[e-mail]>
> Cc: Geert Uytterhoeven <[e-mail]>; Andrzej Hajda <[e-mail]>; Neil
> Armstrong <[e-mail]>; Robert Foss <[e-mail]>; laurent.pinchart
> <[e-mail]>; Jonas Karlman <[e-mail]>; Jernej Skrabec
> <[e-mail]>; David Airlie <[e-mail]>; Simona Vetter <[e-mail]>; Maarten
> Lankhorst <[e-mail]>; Maxime Ripard <[e-mail]>; Thomas Zimmermann
> <[e-mail]>; Rob Herring <[e-mail]>; Krzysztof Kozlowski <[e-mail]>; Conor
> Dooley <[e-mail]>; Mauro Carvalho Chehab <[e-mail]>; Kieran Bingham
> <[e-mail]>; Stephen Boyd <[e-mail]>; Philipp Zabel
> <[e-mail]>; [e-mail]; [e-mail]; linux-renesas-
> [e-mail]; [e-mail]; [e-mail]; Fabrizio Castro
> <[e-mail]>; Prabhakar Mahadev Lad <[e-mail]>
> Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support
> 
> Hi Biju,
> 
> Thank you for the review.
> 
> On Mon, Mar 31, 2025 at 1:38 PM Biju Das <[e-mail]> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <[e-mail]>
> > > Sent: 30 March 2025 22:07
> > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data
> > > support
> > >
> > > From: Lad Prabhakar <[e-mail]>
> > >
> > > In preparation for adding support for the Renesas RZ/V2H(P) SoC,
> > > this patch introduces a mechanism to pass SoC-specific information
> > > via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-
> specific requirements without hardcoding configurations.
> > >
> > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to
> > > the one on the RZ/G2L SoC. While the LINK registers are shared
> > > between the two SoCs, the D-PHY registers differ. Also the VCLK
> > > range differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info`
> is introduced and as now passed as OF data.
> > >
> > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC
> > > support by allowing SoC-specific data to be passed through OF.
> > >
> <snip>
> > > +
> > >       ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
> > >       if (ret < 0)
> > >               return dev_err_probe(dsi->dev, ret, @@ -729,10 +750,12
> > > @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> > >       if (IS_ERR(dsi->vclk))
> > >               return PTR_ERR(dsi->vclk);
> > >
> > > -     dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
> > > -     if (IS_ERR(dsi->rstc))
> > > -             return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> > > -                                  "failed to get rst\n");
> > > +     if (dsi->info->has_dphy_rstc) {
> > > +             dsi->rstc = devm_reset_control_get_exclusive(dsi->dev,
> > > + "rst");
> >
> > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc.
> >
> As the dtbs_check doesn't enforce this,  `has_dphy_rstc` flag was added. Recently the same was done
> for the CRU [0] based on the recent comment received.
> 

RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning, right?

Cheers,
Biju

Prabhakar March 31, 2025, 2:44 p.m. UTC | #4

Hi Biju,

On Mon, Mar 31, 2025 at 3:14 PM Biju Das <[e-mail]> wrote:
>
>
>
> > -----Original Message-----
> > From: Lad, Prabhakar <[e-mail]>
> > Sent: 31 March 2025 14:59
> > To: Biju Das <[e-mail]>
> > Cc: Geert Uytterhoeven <[e-mail]>; Andrzej Hajda <[e-mail]>; Neil
> > Armstrong <[e-mail]>; Robert Foss <[e-mail]>; laurent.pinchart
> > <[e-mail]>; Jonas Karlman <[e-mail]>; Jernej Skrabec
> > <[e-mail]>; David Airlie <[e-mail]>; Simona Vetter <[e-mail]>; Maarten
> > Lankhorst <[e-mail]>; Maxime Ripard <[e-mail]>; Thomas Zimmermann
> > <[e-mail]>; Rob Herring <[e-mail]>; Krzysztof Kozlowski <[e-mail]>; Conor
> > Dooley <[e-mail]>; Mauro Carvalho Chehab <[e-mail]>; Kieran Bingham
> > <[e-mail]>; Stephen Boyd <[e-mail]>; Philipp Zabel
> > <[e-mail]>; [e-mail]; [e-mail]; linux-renesas-
> > [e-mail]; [e-mail]; [e-mail]; Fabrizio Castro
> > <[e-mail]>; Prabhakar Mahadev Lad <[e-mail]>
> > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support
> >
> > Hi Biju,
> >
> > Thank you for the review.
> >
> > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <[e-mail]> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <[e-mail]>
> > > > Sent: 30 March 2025 22:07
> > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data
> > > > support
> > > >
> > > > From: Lad Prabhakar <[e-mail]>
> > > >
> > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC,
> > > > this patch introduces a mechanism to pass SoC-specific information
> > > > via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-
> > specific requirements without hardcoding configurations.
> > > >
> > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to
> > > > the one on the RZ/G2L SoC. While the LINK registers are shared
> > > > between the two SoCs, the D-PHY registers differ. Also the VCLK
> > > > range differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info`
> > is introduced and as now passed as OF data.
> > > >
> > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC
> > > > support by allowing SoC-specific data to be passed through OF.
> > > >
> > <snip>
> > > > +
> > > >       ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
> > > >       if (ret < 0)
> > > >               return dev_err_probe(dsi->dev, ret, @@ -729,10 +750,12
> > > > @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> > > >       if (IS_ERR(dsi->vclk))
> > > >               return PTR_ERR(dsi->vclk);
> > > >
> > > > -     dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
> > > > -     if (IS_ERR(dsi->rstc))
> > > > -             return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> > > > -                                  "failed to get rst\n");
> > > > +     if (dsi->info->has_dphy_rstc) {
> > > > +             dsi->rstc = devm_reset_control_get_exclusive(dsi->dev,
> > > > + "rst");
> > >
> > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc.
> > >
> > As the dtbs_check doesn't enforce this,  `has_dphy_rstc` flag was added. Recently the same was done
> > for the CRU [0] based on the recent comment received.
> >
>
> RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning, right?
>
No we dont [0], note DT binding is written based on the recent
feedback received.

[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[e-mail]/

Cheers,
Prabhakar

Biju Das March 31, 2025, 3:04 p.m. UTC | #5

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <[e-mail]>
> Sent: 31 March 2025 15:44
> Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support
> 
> Hi Biju,
> 
> On Mon, Mar 31, 2025 at 3:14 PM Biju Das <[e-mail]> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Lad, Prabhakar <[e-mail]>
> > > Sent: 31 March 2025 14:59
> > > To: Biju Das <[e-mail]>
> > > Cc: Geert Uytterhoeven <[e-mail]>; Andrzej Hajda
> > > <[e-mail]>; Neil Armstrong
> > > <[e-mail]>; Robert Foss <[e-mail]>;
> > > laurent.pinchart <[e-mail]>; Jonas Karlman
> > > <[e-mail]>; Jernej Skrabec <[e-mail]>; David
> > > Airlie <[e-mail]>; Simona Vetter <[e-mail]>; Maarten
> > > Lankhorst <[e-mail]>; Maxime Ripard
> > > <[e-mail]>; Thomas Zimmermann <[e-mail]>; Rob
> > > Herring <[e-mail]>; Krzysztof Kozlowski <[e-mail]>;
> > > Conor Dooley <[e-mail]>; Mauro Carvalho Chehab
> > > <[e-mail]>; Kieran Bingham
> > > <[e-mail]>; Stephen Boyd
> > > <[e-mail]>; Philipp Zabel <[e-mail]>;
> > > [e-mail]; [e-mail];
> > > linux-renesas- [e-mail]; [e-mail];
> > > [e-mail]; Fabrizio Castro
> > > <[e-mail]>; Prabhakar Mahadev Lad
> > > <[e-mail]>
> > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF
> > > data support
> > >
> > > Hi Biju,
> > >
> > > Thank you for the review.
> > >
> > > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <[e-mail]> wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Thanks for the patch.
> > > >
> > > > > -----Original Message-----
> > > > > From: Prabhakar <[e-mail]>
> > > > > Sent: 30 March 2025 22:07
> > > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF
> > > > > data support
> > > > >
> > > > > From: Lad Prabhakar <[e-mail]>
> > > > >
> > > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC,
> > > > > this patch introduces a mechanism to pass SoC-specific
> > > > > information via OF data in the DSI driver. This enables the
> > > > > driver to adapt dynamically to various SoC-
> > > specific requirements without hardcoding configurations.
> > > > >
> > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical
> > > > > to the one on the RZ/G2L SoC. While the LINK registers are
> > > > > shared between the two SoCs, the D-PHY registers differ. Also
> > > > > the VCLK range differs on both these SoCs. To accommodate these
> > > > > differences `struct rzg2l_mipi_dsi_hw_info`
> > > is introduced and as now passed as OF data.
> > > > >
> > > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC
> > > > > support by allowing SoC-specific data to be passed through OF.
> > > > >
> > > <snip>
> > > > > +
> > > > >       ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
> > > > >       if (ret < 0)
> > > > >               return dev_err_probe(dsi->dev, ret, @@ -729,10
> > > > > +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> > > > >       if (IS_ERR(dsi->vclk))
> > > > >               return PTR_ERR(dsi->vclk);
> > > > >
> > > > > -     dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
> > > > > -     if (IS_ERR(dsi->rstc))
> > > > > -             return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> > > > > -                                  "failed to get rst\n");
> > > > > +     if (dsi->info->has_dphy_rstc) {
> > > > > +             dsi->rstc =
> > > > > + devm_reset_control_get_exclusive(dsi->dev,
> > > > > + "rst");
> > > >
> > > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc.
> > > >
> > > As the dtbs_check doesn't enforce this,  `has_dphy_rstc` flag was
> > > added. Recently the same was done for the CRU [0] based on the recent comment received.
> > >
> >
> > RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning,
> right?
> >
> No we dont [0], note DT binding is written based on the recent feedback received.

That is strange. It is triggering warning for me, if I just update the example.

	from schema $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
/home/biju/rzg3e-linux-renesas/Documentation/devicetree/bindings/display/bridge/renesas,dsi.example.dtb: dsi@10850000: reset-names: ['rst', 'arst', 'prst'] is too long
	from schema $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#


[1]
     dsi0: dsi@10850000 {
-        compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
+        compatible = "renesas,r9a09g057-mipi-dsi";
         reg = <0x10850000 0x20000>;
         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
@@ -205,12 +205,11 @@ examples:
         interrupt-names = "seq0", "seq1", "vin1", "rcv",
                           "ferr", "ppi", "debug";
         clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
-                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
-        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+        clock-names = "pllclk", "aclk", "pclk", "vclk", "lpclk";
        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
        reset-names = "rst", "arst", "prst";

Cheers,
Biju
> 
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20250330210717.46080-7-
> [e-mail]/
> 
> Cheers,
> Prabhakar

Prabhakar March 31, 2025, 3:27 p.m. UTC | #6

Hi Biju,

On Mon, Mar 31, 2025 at 4:04 PM Biju Das <[e-mail]> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Lad, Prabhakar <[e-mail]>
> > Sent: 31 March 2025 15:44
> > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support
> >
> > Hi Biju,
> >
> > On Mon, Mar 31, 2025 at 3:14 PM Biju Das <[e-mail]> wrote:
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Lad, Prabhakar <[e-mail]>
> > > > Sent: 31 March 2025 14:59
> > > > To: Biju Das <[e-mail]>
> > > > Cc: Geert Uytterhoeven <[e-mail]>; Andrzej Hajda
> > > > <[e-mail]>; Neil Armstrong
> > > > <[e-mail]>; Robert Foss <[e-mail]>;
> > > > laurent.pinchart <[e-mail]>; Jonas Karlman
> > > > <[e-mail]>; Jernej Skrabec <[e-mail]>; David
> > > > Airlie <[e-mail]>; Simona Vetter <[e-mail]>; Maarten
> > > > Lankhorst <[e-mail]>; Maxime Ripard
> > > > <[e-mail]>; Thomas Zimmermann <[e-mail]>; Rob
> > > > Herring <[e-mail]>; Krzysztof Kozlowski <[e-mail]>;
> > > > Conor Dooley <[e-mail]>; Mauro Carvalho Chehab
> > > > <[e-mail]>; Kieran Bingham
> > > > <[e-mail]>; Stephen Boyd
> > > > <[e-mail]>; Philipp Zabel <[e-mail]>;
> > > > [e-mail]; [e-mail];
> > > > linux-renesas- [e-mail]; [e-mail];
> > > > [e-mail]; Fabrizio Castro
> > > > <[e-mail]>; Prabhakar Mahadev Lad
> > > > <[e-mail]>
> > > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF
> > > > data support
> > > >
> > > > Hi Biju,
> > > >
> > > > Thank you for the review.
> > > >
> > > > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <[e-mail]> wrote:
> > > > >
> > > > > Hi Prabhakar,
> > > > >
> > > > > Thanks for the patch.
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Prabhakar <[e-mail]>
> > > > > > Sent: 30 March 2025 22:07
> > > > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF
> > > > > > data support
> > > > > >
> > > > > > From: Lad Prabhakar <[e-mail]>
> > > > > >
> > > > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC,
> > > > > > this patch introduces a mechanism to pass SoC-specific
> > > > > > information via OF data in the DSI driver. This enables the
> > > > > > driver to adapt dynamically to various SoC-
> > > > specific requirements without hardcoding configurations.
> > > > > >
> > > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical
> > > > > > to the one on the RZ/G2L SoC. While the LINK registers are
> > > > > > shared between the two SoCs, the D-PHY registers differ. Also
> > > > > > the VCLK range differs on both these SoCs. To accommodate these
> > > > > > differences `struct rzg2l_mipi_dsi_hw_info`
> > > > is introduced and as now passed as OF data.
> > > > > >
> > > > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC
> > > > > > support by allowing SoC-specific data to be passed through OF.
> > > > > >
> > > > <snip>
> > > > > > +
> > > > > >       ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
> > > > > >       if (ret < 0)
> > > > > >               return dev_err_probe(dsi->dev, ret, @@ -729,10
> > > > > > +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> > > > > >       if (IS_ERR(dsi->vclk))
> > > > > >               return PTR_ERR(dsi->vclk);
> > > > > >
> > > > > > -     dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
> > > > > > -     if (IS_ERR(dsi->rstc))
> > > > > > -             return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> > > > > > -                                  "failed to get rst\n");
> > > > > > +     if (dsi->info->has_dphy_rstc) {
> > > > > > +             dsi->rstc =
> > > > > > + devm_reset_control_get_exclusive(dsi->dev,
> > > > > > + "rst");
> > > > >
> > > > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc.
> > > > >
> > > > As the dtbs_check doesn't enforce this,  `has_dphy_rstc` flag was
> > > > added. Recently the same was done for the CRU [0] based on the recent comment received.
> > > >
> > >
> > > RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning,
> > right?
> > >
> > No we dont [0], note DT binding is written based on the recent feedback received.
>
> That is strange. It is triggering warning for me, if I just update the example.
>
Ahh right I missed that. The current implementation is based on this
comment received [0] (same being applied for reset). Please let me
know if you still want me to use
devm_reset_control_get_optional_exclusive() (and same for the clk).

[0] https://lore.kernel.org/lkml/[e-mail]/

Cheers,
Prabhakar

Biju Das April 1, 2025, 5:23 a.m. UTC | #7

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <[e-mail]>
> Sent: 31 March 2025 16:27
> Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support
> 
> Hi Biju,
> 
> On Mon, Mar 31, 2025 at 4:04 PM Biju Das <[e-mail]> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Lad, Prabhakar <[e-mail]>
> > > Sent: 31 March 2025 15:44
> > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF
> > > data support
> > >
> > > Hi Biju,
> > >
> > > On Mon, Mar 31, 2025 at 3:14 PM Biju Das <[e-mail]> wrote:
> > > >
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Lad, Prabhakar <[e-mail]>
> > > > > Sent: 31 March 2025 14:59
> > > > > To: Biju Das <[e-mail]>
> > > > > Cc: Geert Uytterhoeven <[e-mail]>; Andrzej Hajda
> > > > > <[e-mail]>; Neil Armstrong
> > > > > <[e-mail]>; Robert Foss <[e-mail]>;
> > > > > laurent.pinchart <[e-mail]>; Jonas
> > > > > Karlman <[e-mail]>; Jernej Skrabec
> > > > > <[e-mail]>; David Airlie <[e-mail]>;
> > > > > Simona Vetter <[e-mail]>; Maarten Lankhorst
> > > > > <[e-mail]>; Maxime Ripard
> > > > > <[e-mail]>; Thomas Zimmermann <[e-mail]>;
> > > > > Rob Herring <[e-mail]>; Krzysztof Kozlowski
> > > > > <[e-mail]>; Conor Dooley <[e-mail]>; Mauro
> > > > > Carvalho Chehab <[e-mail]>; Kieran Bingham
> > > > > <[e-mail]>; Stephen Boyd
> > > > > <[e-mail]>; Philipp Zabel <[e-mail]>;
> > > > > [e-mail]; [e-mail];
> > > > > linux-renesas- [e-mail]; [e-mail];
> > > > > [e-mail]; Fabrizio Castro
> > > > > <[e-mail]>; Prabhakar Mahadev Lad
> > > > > <[e-mail]>
> > > > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF
> > > > > data support
> > > > >
> > > > > Hi Biju,
> > > > >
> > > > > Thank you for the review.
> > > > >
> > > > > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <[e-mail]> wrote:
> > > > > >
> > > > > > Hi Prabhakar,
> > > > > >
> > > > > > Thanks for the patch.
> > > > > >
> > > > > > > -----Original Message-----
> > > > > > > From: Prabhakar <[e-mail]>
> > > > > > > Sent: 30 March 2025 22:07
> > > > > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF
> > > > > > > data support
> > > > > > >
> > > > > > > From: Lad Prabhakar
> > > > > > > <[e-mail]>
> > > > > > >
> > > > > > > In preparation for adding support for the Renesas RZ/V2H(P)
> > > > > > > SoC, this patch introduces a mechanism to pass SoC-specific
> > > > > > > information via OF data in the DSI driver. This enables the
> > > > > > > driver to adapt dynamically to various SoC-
> > > > > specific requirements without hardcoding configurations.
> > > > > > >
> > > > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly
> > > > > > > identical to the one on the RZ/G2L SoC. While the LINK
> > > > > > > registers are shared between the two SoCs, the D-PHY
> > > > > > > registers differ. Also the VCLK range differs on both these
> > > > > > > SoCs. To accommodate these differences `struct
> > > > > > > rzg2l_mipi_dsi_hw_info`
> > > > > is introduced and as now passed as OF data.
> > > > > > >
> > > > > > > These changes lay the groundwork for the upcoming RZ/V2H(P)
> > > > > > > SoC support by allowing SoC-specific data to be passed through OF.
> > > > > > >
> > > > > <snip>
> > > > > > > +
> > > > > > >       ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
> > > > > > >       if (ret < 0)
> > > > > > >               return dev_err_probe(dsi->dev, ret, @@ -729,10
> > > > > > > +750,12 @@ static int rzg2l_mipi_dsi_probe(struct
> > > > > > > +platform_device *pdev)
> > > > > > >       if (IS_ERR(dsi->vclk))
> > > > > > >               return PTR_ERR(dsi->vclk);
> > > > > > >
> > > > > > > -     dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
> > > > > > > -     if (IS_ERR(dsi->rstc))
> > > > > > > -             return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
> > > > > > > -                                  "failed to get rst\n");
> > > > > > > +     if (dsi->info->has_dphy_rstc) {
> > > > > > > +             dsi->rstc =
> > > > > > > + devm_reset_control_get_exclusive(dsi->dev,
> > > > > > > + "rst");
> > > > > >
> > > > > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc.
> > > > > >
> > > > > As the dtbs_check doesn't enforce this,  `has_dphy_rstc` flag
> > > > > was added. Recently the same was done for the CRU [0] based on the recent comment received.
> > > > >
> > > >
> > > > RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then
> > > > you should get dtbs warning,
> > > right?
> > > >
> > > No we dont [0], note DT binding is written based on the recent feedback received.
> >
> > That is strange. It is triggering warning for me, if I just update the example.
> >
> Ahh right I missed that. The current implementation is based on this comment received [0] (same being
> applied for reset). Please let me know if you still want me to use
> devm_reset_control_get_optional_exclusive() (and same for the clk).

Both OK to me. As DT binding validates optional resets, I would avoid redundant check in
driver as it is anyway like no-op with optional calls.

Cheers,
Biju

Patch

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index e0379f099659..44b95082b29c 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -28,10 +28,24 @@ 
 
 #include "rzg2l_mipi_dsi_regs.h"
 
+struct rzg2l_mipi_dsi;
+
+struct rzg2l_mipi_dsi_hw_info {
+	int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq);
+	void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
+	u32 phy_reg_offset;
+	u32 link_reg_offset;
+	unsigned long max_dclk;
+	unsigned long min_dclk;
+	bool has_dphy_rstc;
+};
+
 struct rzg2l_mipi_dsi {
 	struct device *dev;
 	void __iomem *mmio;
 
+	const struct rzg2l_mipi_dsi_hw_info *info;
+
 	struct reset_control *rstc;
 	struct reset_control *arstc;
 	struct reset_control *prstc;
@@ -164,22 +178,22 @@  static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = {
 
 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
 {
-	iowrite32(data, dsi->mmio + reg);
+	iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg);
 }
 
 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
 {
-	iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg);
+	iowrite32(data, dsi->mmio + dsi->info->link_reg_offset + reg);
 }
 
 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
 {
-	return ioread32(dsi->mmio + reg);
+	return ioread32(dsi->mmio + dsi->info->phy_reg_offset + reg);
 }
 
 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
 {
-	return ioread32(dsi->mmio + LINK_REG_OFFSET + reg);
+	return ioread32(dsi->mmio + dsi->info->link_reg_offset + reg);
 }
 
 /* -----------------------------------------------------------------------------
@@ -291,7 +305,7 @@  static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
 	vclk_rate = clk_get_rate(dsi->vclk);
 	hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes);
 
-	ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq);
+	ret = dsi->info->dphy_init(dsi, hsfreq);
 	if (ret < 0)
 		goto err_phy;
 
@@ -334,7 +348,7 @@  static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
 	return 0;
 
 err_phy:
-	rzg2l_mipi_dsi_dphy_exit(dsi);
+	dsi->info->dphy_exit(dsi);
 	pm_runtime_put(dsi->dev);
 
 	return ret;
@@ -342,7 +356,7 @@  static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
 
 static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi)
 {
-	rzg2l_mipi_dsi_dphy_exit(dsi);
+	dsi->info->dphy_exit(dsi);
 	pm_runtime_put(dsi->dev);
 }
 
@@ -585,10 +599,12 @@  rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
 				 const struct drm_display_info *info,
 				 const struct drm_display_mode *mode)
 {
-	if (mode->clock > 148500)
+	struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
+
+	if (mode->clock > dsi->info->max_dclk)
 		return MODE_CLOCK_HIGH;
 
-	if (mode->clock < 5803)
+	if (mode->clock < dsi->info->min_dclk)
 		return MODE_CLOCK_LOW;
 
 	return MODE_OK;
@@ -714,6 +730,11 @@  static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, dsi);
 	dsi->dev = &pdev->dev;
 
+	dsi->info = of_device_get_match_data(&pdev->dev);
+	if (!dsi->info)
+		return dev_err_probe(dsi->dev, -ENODEV,
+				     "missing data info\n");
+
 	ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
 	if (ret < 0)
 		return dev_err_probe(dsi->dev, ret,
@@ -729,10 +750,12 @@  static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
 	if (IS_ERR(dsi->vclk))
 		return PTR_ERR(dsi->vclk);
 
-	dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
-	if (IS_ERR(dsi->rstc))
-		return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
-				     "failed to get rst\n");
+	if (dsi->info->has_dphy_rstc) {
+		dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
+		if (IS_ERR(dsi->rstc))
+			return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
+					     "failed to get rst\n");
+	}
 
 	dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst");
 	if (IS_ERR(dsi->arstc))
@@ -757,13 +780,13 @@  static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
 	 * mode->clock and format are not available. So initialize DPHY with
 	 * timing parameters for 80Mbps.
 	 */
-	ret = rzg2l_mipi_dsi_dphy_init(dsi, 80000000);
+	ret = dsi->info->dphy_init(dsi, 80000000);
 	if (ret < 0)
 		goto err_phy;
 
 	txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR);
 	dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes);
-	rzg2l_mipi_dsi_dphy_exit(dsi);
+	dsi->info->dphy_exit(dsi);
 	pm_runtime_put(dsi->dev);
 
 	/* Initialize the DRM bridge. */
@@ -780,7 +803,7 @@  static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
 	return 0;
 
 err_phy:
-	rzg2l_mipi_dsi_dphy_exit(dsi);
+	dsi->info->dphy_exit(dsi);
 	pm_runtime_put(dsi->dev);
 err_pm_disable:
 	pm_runtime_disable(dsi->dev);
@@ -795,8 +818,17 @@  static void rzg2l_mipi_dsi_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 }
 
+static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = {
+	.dphy_init = rzg2l_mipi_dsi_dphy_init,
+	.dphy_exit = rzg2l_mipi_dsi_dphy_exit,
+	.has_dphy_rstc = true,
+	.link_reg_offset = 0x10000,
+	.max_dclk = 148500,
+	.min_dclk = 5803,
+};
+
 static const struct of_device_id rzg2l_mipi_dsi_of_table[] = {
-	{ .compatible = "renesas,rzg2l-mipi-dsi" },
+	{ .compatible = "renesas,rzg2l-mipi-dsi", .data = &rzg2l_mipi_dsi_info, },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
index 1dbc16ec64a4..16efe4dc59f4 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
@@ -41,8 +41,6 @@ 
 #define DSIDPHYTIM3_THS_ZERO(x)		((x) << 0)
 
 /* --------------------------------------------------------*/
-/* Link Registers */
-#define LINK_REG_OFFSET			0x10000
 
 /* Link Status Register */
 #define LINKSR				0x10